* [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series
@ 2023-06-25 12:03 Nicholas Piggin
2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Nicholas Piggin @ 2023-06-25 12:03 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Cédric Le Goater, Harsh Prateek Bora
Cedric kindly reviewed these already so I think they should be
good to go now. This is just a rebase and slight rewording the
changelog. Still haven't completed the main chiptod device yet.
Thanks,
Nick
Nicholas Piggin (2):
target/ppc: Tidy POWER book4 SPR registration
target/ppc: Add TFMR SPR implementation with read and write helpers
target/ppc/cpu_init.c | 82 ++++++++++++++++++++++++------------
target/ppc/helper.h | 2 +
target/ppc/spr_common.h | 2 +
target/ppc/timebase_helper.c | 13 ++++++
target/ppc/translate.c | 10 +++++
5 files changed, 82 insertions(+), 27 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration 2023-06-25 12:03 [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Nicholas Piggin @ 2023-06-25 12:03 ` Nicholas Piggin 2023-06-30 19:36 ` Daniel Henrique Barboza 2023-06-25 12:03 ` [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers Nicholas Piggin 2023-06-29 4:58 ` [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Cédric Le Goater 2 siblings, 1 reply; 9+ messages in thread From: Nicholas Piggin @ 2023-06-25 12:03 UTC (permalink / raw) To: qemu-devel Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Cédric Le Goater, Harsh Prateek Bora POWER book4 (implementation-specific) SPRs are sometimes in their own functions, but in other cases are mixed with architected SPRs. Do some spring cleaning on these. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++-------------- 1 file changed, 55 insertions(+), 27 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a97fb7fe10..21ff4861c3 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env) &spr_read_generic, SPR_NOACCESS, &spr_read_generic, NULL, 0x00000000); - spr_register_hv(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TSCR, "TSCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, - 0x00000000); - spr_register_hv(env, SPR_HMER, "HMER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_hmer, - 0x00000000); - spr_register_hv(env, SPR_HMEER, "HMEER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TFMR, "TFMR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); spr_register_hv(env, SPR_LPIDR, "LPIDR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, @@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env) #endif } +/* SPRs specific to IBM POWER CPUs */ +static void register_power_common_book4_sprs(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TSCR, "TSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, + 0x00000000); + spr_register_hv(env, SPR_HMER, "HMER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_hmer, + 0x00000000); + spr_register_hv(env, SPR_HMEER, "HMEER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TFMR, "TFMR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#endif +} + +static void register_power9_book4_sprs(CPUPPCState *env) +{ + /* Add a number of P9 book4 registers */ + register_power_common_book4_sprs(env); +#if !defined(CONFIG_USER_ONLY) + spr_register_kvm(env, SPR_WORT, "WORT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_WORT, 0); +#endif +} + static void register_power8_book4_sprs(CPUPPCState *env) { /* Add a number of P8 book4 registers */ + register_power_common_book4_sprs(env); #if !defined(CONFIG_USER_ONLY) spr_register_kvm(env, SPR_ACOP, "ACOP", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); + /* PID is only in BookE in ISA v2.07 */ spr_register_kvm(env, SPR_BOOKS_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pidr, @@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env) { /* Add a number of P7 book4 registers */ #if !defined(CONFIG_USER_ONLY) + register_power_common_book4_sprs(env); spr_register_kvm(env, SPR_ACOP, "ACOP", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); + /* PID is only in BookE in ISA v2.06 */ spr_register_kvm(env, SPR_BOOKS_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic32, @@ -5716,6 +5739,11 @@ static void register_power9_mmu_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x0000000000000000); + /* PID is part of the BookS ISA from v3.0 */ + spr_register_kvm(env, SPR_BOOKS_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pidr, + KVM_REG_PPC_PID, 0); #endif } @@ -6269,7 +6297,7 @@ static void init_proc_POWER9(CPUPPCState *env) register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); - register_power8_book4_sprs(env); + register_power9_book4_sprs(env); register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); @@ -6462,7 +6490,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); - register_power8_book4_sprs(env); + register_power9_book4_sprs(env); register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); register_power10_hash_sprs(env); -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration 2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin @ 2023-06-30 19:36 ` Daniel Henrique Barboza 0 siblings, 0 replies; 9+ messages in thread From: Daniel Henrique Barboza @ 2023-06-30 19:36 UTC (permalink / raw) To: Nicholas Piggin, qemu-devel Cc: qemu-ppc, Cédric Le Goater, Harsh Prateek Bora On 6/25/23 09:03, Nicholas Piggin wrote: > POWER book4 (implementation-specific) SPRs are sometimes in their own > functions, but in other cases are mixed with architected SPRs. Do some > spring cleaning on these. > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel > target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++-------------- > 1 file changed, 55 insertions(+), 27 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index a97fb7fe10..21ff4861c3 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env) > &spr_read_generic, SPR_NOACCESS, > &spr_read_generic, NULL, > 0x00000000); > - spr_register_hv(env, SPR_HID0, "HID0", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > - spr_register_hv(env, SPR_TSCR, "TSCR", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic32, > - 0x00000000); > - spr_register_hv(env, SPR_HMER, "HMER", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_hmer, > - 0x00000000); > - spr_register_hv(env, SPR_HMEER, "HMEER", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > - spr_register_hv(env, SPR_TFMR, "TFMR", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > spr_register_hv(env, SPR_LPIDR, "LPIDR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > @@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env) > #endif > } > > +/* SPRs specific to IBM POWER CPUs */ > +static void register_power_common_book4_sprs(CPUPPCState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + spr_register_hv(env, SPR_HID0, "HID0", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TSCR, "TSCR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic32, > + 0x00000000); > + spr_register_hv(env, SPR_HMER, "HMER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_hmer, > + 0x00000000); > + spr_register_hv(env, SPR_HMEER, "HMEER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TFMR, "TFMR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > +#endif > +} > + > +static void register_power9_book4_sprs(CPUPPCState *env) > +{ > + /* Add a number of P9 book4 registers */ > + register_power_common_book4_sprs(env); > +#if !defined(CONFIG_USER_ONLY) > + spr_register_kvm(env, SPR_WORT, "WORT", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_WORT, 0); > +#endif > +} > + > static void register_power8_book4_sprs(CPUPPCState *env) > { > /* Add a number of P8 book4 registers */ > + register_power_common_book4_sprs(env); > #if !defined(CONFIG_USER_ONLY) > spr_register_kvm(env, SPR_ACOP, "ACOP", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_ACOP, 0); > + /* PID is only in BookE in ISA v2.07 */ > spr_register_kvm(env, SPR_BOOKS_PID, "PID", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_pidr, > @@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env) > { > /* Add a number of P7 book4 registers */ > #if !defined(CONFIG_USER_ONLY) > + register_power_common_book4_sprs(env); > spr_register_kvm(env, SPR_ACOP, "ACOP", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_ACOP, 0); > + /* PID is only in BookE in ISA v2.06 */ > spr_register_kvm(env, SPR_BOOKS_PID, "PID", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic32, > @@ -5716,6 +5739,11 @@ static void register_power9_mmu_sprs(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x0000000000000000); > + /* PID is part of the BookS ISA from v3.0 */ > + spr_register_kvm(env, SPR_BOOKS_PID, "PID", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_pidr, > + KVM_REG_PPC_PID, 0); > #endif > } > > @@ -6269,7 +6297,7 @@ static void init_proc_POWER9(CPUPPCState *env) > register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > - register_power8_book4_sprs(env); > + register_power9_book4_sprs(env); > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > > @@ -6462,7 +6490,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > - register_power8_book4_sprs(env); > + register_power9_book4_sprs(env); > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > register_power10_hash_sprs(env); ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers 2023-06-25 12:03 [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Nicholas Piggin 2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin @ 2023-06-25 12:03 ` Nicholas Piggin 2023-06-30 19:36 ` Daniel Henrique Barboza 2023-06-29 4:58 ` [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Cédric Le Goater 2 siblings, 1 reply; 9+ messages in thread From: Nicholas Piggin @ 2023-06-25 12:03 UTC (permalink / raw) To: qemu-devel Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Cédric Le Goater, Harsh Prateek Bora TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for now behaviour is unchanged. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/cpu_init.c | 2 +- target/ppc/helper.h | 2 ++ target/ppc/spr_common.h | 2 ++ target/ppc/timebase_helper.c | 13 +++++++++++++ target/ppc/translate.c | 10 ++++++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 21ff4861c3..7d1b148fd4 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5658,7 +5658,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_TFMR, "TFMR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_tfmr, &spr_write_tfmr, 0x00000000); #endif } diff --git a/target/ppc/helper.h b/target/ppc/helper.h index fda40b8a60..eac5e7ab5d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -745,6 +745,8 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_1(load_tfmr, tl, env) +DEF_HELPER_2(store_tfmr, void, env, tl) DEF_HELPER_3(store_ibatl, void, env, i32, tl) DEF_HELPER_3(store_ibatu, void, env, i32, tl) DEF_HELPER_3(store_dbatl, void, env, i32, tl) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 4c0f2bed77..fbf52123b5 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -194,6 +194,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gprn); void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); #endif diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index b80f56af7e..08a6b47ee0 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -144,6 +144,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) store_booke_tsr(env, val); } +#if defined(TARGET_PPC64) +/* POWER processor Timebase Facility */ +target_ulong helper_load_tfmr(CPUPPCState *env) +{ + return env->spr[SPR_TFMR]; +} + +void helper_store_tfmr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_TFMR] = val; +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index eb278c2683..9ce03344de 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1175,6 +1175,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); +} + +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); +} + void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers 2023-06-25 12:03 ` [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers Nicholas Piggin @ 2023-06-30 19:36 ` Daniel Henrique Barboza 0 siblings, 0 replies; 9+ messages in thread From: Daniel Henrique Barboza @ 2023-06-30 19:36 UTC (permalink / raw) To: Nicholas Piggin, qemu-devel Cc: qemu-ppc, Cédric Le Goater, Harsh Prateek Bora On 6/25/23 09:03, Nicholas Piggin wrote: > TFMR is the Time Facility Management Register which is specific to > POWER CPUs, and used for the purpose of timebase management (generally > by firmware, not the OS). > > Add helpers for the TFMR register, which will form part of the core > timebase facility model in future but for now behaviour is unchanged. > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Queued in gitlab.com/danielhb/qemu/tree/ppc-next after amending this qemu-system-ppc build error: diff --git a/target/ppc/helper.h b/target/ppc/helper.h index eac5e7ab5d..828f7844c8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -722,6 +722,8 @@ DEF_HELPER_FLAGS_1(load_dpdes, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_dpdes, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(book3s_msgsndp, void, env, tl) DEF_HELPER_2(book3s_msgclrp, void, env, tl) +DEF_HELPER_1(load_tfmr, tl, env) +DEF_HELPER_2(store_tfmr, void, env, tl) #endif DEF_HELPER_2(store_sdr1, void, env, tl) DEF_HELPER_2(store_pidr, void, env, tl) @@ -745,8 +747,6 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_1(load_tfmr, tl, env) -DEF_HELPER_2(store_tfmr, void, env, tl) DEF_HELPER_3(store_ibatl, void, env, i32, tl) DEF_HELPER_3(store_ibatu, void, env, i32, tl) DEF_HELPER_3(store_dbatl, void, env, i32, tl) Daniel > target/ppc/cpu_init.c | 2 +- > target/ppc/helper.h | 2 ++ > target/ppc/spr_common.h | 2 ++ > target/ppc/timebase_helper.c | 13 +++++++++++++ > target/ppc/translate.c | 10 ++++++++++ > 5 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 21ff4861c3..7d1b148fd4 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5658,7 +5658,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_TFMR, "TFMR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_tfmr, &spr_write_tfmr, > 0x00000000); > #endif > } > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index fda40b8a60..eac5e7ab5d 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -745,6 +745,8 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) > DEF_HELPER_2(store_40x_sler, void, env, tl) > DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) > DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) > +DEF_HELPER_1(load_tfmr, tl, env) > +DEF_HELPER_2(store_tfmr, void, env, tl) > DEF_HELPER_3(store_ibatl, void, env, i32, tl) > DEF_HELPER_3(store_ibatu, void, env, i32, tl) > DEF_HELPER_3(store_dbatl, void, env, i32, tl) > diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h > index 4c0f2bed77..fbf52123b5 100644 > --- a/target/ppc/spr_common.h > +++ b/target/ppc/spr_common.h > @@ -194,6 +194,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gprn); > void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); > void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); > void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); > +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); > +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); > void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); > #endif > diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c > index b80f56af7e..08a6b47ee0 100644 > --- a/target/ppc/timebase_helper.c > +++ b/target/ppc/timebase_helper.c > @@ -144,6 +144,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) > store_booke_tsr(env, val); > } > > +#if defined(TARGET_PPC64) > +/* POWER processor Timebase Facility */ > +target_ulong helper_load_tfmr(CPUPPCState *env) > +{ > + return env->spr[SPR_TFMR]; > +} > + > +void helper_store_tfmr(CPUPPCState *env, target_ulong val) > +{ > + env->spr[SPR_TFMR] = val; > +} > +#endif > + > /*****************************************************************************/ > /* Embedded PowerPC specific helpers */ > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index eb278c2683..9ce03344de 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -1175,6 +1175,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) > spr_store_dump_spr(sprn); > } > > +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) > +{ > + gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); > +} > + > +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) > +{ > + gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); > +} > + > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) > { > gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series 2023-06-25 12:03 [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Nicholas Piggin 2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin 2023-06-25 12:03 ` [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers Nicholas Piggin @ 2023-06-29 4:58 ` Cédric Le Goater 2023-06-30 19:38 ` Daniel Henrique Barboza 2 siblings, 1 reply; 9+ messages in thread From: Cédric Le Goater @ 2023-06-29 4:58 UTC (permalink / raw) To: Nicholas Piggin, qemu-devel Cc: qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora On 6/25/23 14:03, Nicholas Piggin wrote: > Cedric kindly reviewed these already so I think they should be > good to go now. This is just a rebase and slight rewording the > changelog. Still haven't completed the main chiptod device yet. > > Thanks, > Nick > > Nicholas Piggin (2): > target/ppc: Tidy POWER book4 SPR registration > target/ppc: Add TFMR SPR implementation with read and write helpers > > target/ppc/cpu_init.c | 82 ++++++++++++++++++++++++------------ > target/ppc/helper.h | 2 + > target/ppc/spr_common.h | 2 + > target/ppc/timebase_helper.c | 13 ++++++ > target/ppc/translate.c | 10 +++++ > 5 files changed, 82 insertions(+), 27 deletions(-) > Daniel, When you start building the next PPC PR, I think you can also take this patch : [4/4] target/ppc: Implement core timebase state machine and TFMR https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233612.125879-5-npiggin@gmail.com/ It belongs to the same series. Thanks, C. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series 2023-06-29 4:58 ` [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Cédric Le Goater @ 2023-06-30 19:38 ` Daniel Henrique Barboza 2023-07-01 8:38 ` Nicholas Piggin 0 siblings, 1 reply; 9+ messages in thread From: Daniel Henrique Barboza @ 2023-06-30 19:38 UTC (permalink / raw) To: Cédric Le Goater, Nicholas Piggin, qemu-devel Cc: qemu-ppc, Harsh Prateek Bora On 6/29/23 01:58, Cédric Le Goater wrote: > On 6/25/23 14:03, Nicholas Piggin wrote: >> Cedric kindly reviewed these already so I think they should be >> good to go now. This is just a rebase and slight rewording the >> changelog. Still haven't completed the main chiptod device yet. >> >> Thanks, >> Nick >> >> Nicholas Piggin (2): >> target/ppc: Tidy POWER book4 SPR registration >> target/ppc: Add TFMR SPR implementation with read and write helpers >> >> target/ppc/cpu_init.c | 82 ++++++++++++++++++++++++------------ >> target/ppc/helper.h | 2 + >> target/ppc/spr_common.h | 2 + >> target/ppc/timebase_helper.c | 13 ++++++ >> target/ppc/translate.c | 10 +++++ >> 5 files changed, 82 insertions(+), 27 deletions(-) >> > > > Daniel, > > When you start building the next PPC PR, I think you can also take > this patch : > > [4/4] target/ppc: Implement core timebase state machine and TFMR > https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233612.125879-5-npiggin@gmail.com/ > > It belongs to the same series. That doesn't apply cleanly with these 2 patches and it didn't look trivial to me. As if there were some code missing. If Nick re-send it rebased on top of ppc-next I can queue it. Since it's a rebase you can keep the r-b. Thanks, Daniel > > Thanks, > > C. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series 2023-06-30 19:38 ` Daniel Henrique Barboza @ 2023-07-01 8:38 ` Nicholas Piggin 2023-07-01 9:03 ` Cédric Le Goater 0 siblings, 1 reply; 9+ messages in thread From: Nicholas Piggin @ 2023-07-01 8:38 UTC (permalink / raw) To: Daniel Henrique Barboza, Cédric Le Goater, qemu-devel Cc: qemu-ppc, Harsh Prateek Bora On Sat Jul 1, 2023 at 5:38 AM AEST, Daniel Henrique Barboza wrote: > > > On 6/29/23 01:58, Cédric Le Goater wrote: > > On 6/25/23 14:03, Nicholas Piggin wrote: > >> Cedric kindly reviewed these already so I think they should be > >> good to go now. This is just a rebase and slight rewording the > >> changelog. Still haven't completed the main chiptod device yet. > >> > >> Thanks, > >> Nick > >> > >> Nicholas Piggin (2): > >> target/ppc: Tidy POWER book4 SPR registration > >> target/ppc: Add TFMR SPR implementation with read and write helpers > >> > >> target/ppc/cpu_init.c | 82 ++++++++++++++++++++++++------------ > >> target/ppc/helper.h | 2 + > >> target/ppc/spr_common.h | 2 + > >> target/ppc/timebase_helper.c | 13 ++++++ > >> target/ppc/translate.c | 10 +++++ > >> 5 files changed, 82 insertions(+), 27 deletions(-) > >> > > > > > > Daniel, > > > > When you start building the next PPC PR, I think you can also take > > this patch : > > > > [4/4] target/ppc: Implement core timebase state machine and TFMR > > https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233612.125879-5-npiggin@gmail.com/ > > > > It belongs to the same series. > > That doesn't apply cleanly with these 2 patches and it didn't look trivial to > me. As if there were some code missing. Yeah, it actually uses some signals from the nest chiptod patch. > If Nick re-send it rebased on top of ppc-next I can queue it. Since it's a > rebase you can keep the r-b. Thanks, I'll see how it goes, it may have to wait for next merge. SMT for powernv is a little more important since it's more user-facing and it would be nice to introduce SMT for both pseries and powernv together. Chiptod for doesn't really do much except step through skiboot init code, and getting more useful things wired up like TB fault / HMI injection won't be ready before freeze. Thanks, Nick ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series 2023-07-01 8:38 ` Nicholas Piggin @ 2023-07-01 9:03 ` Cédric Le Goater 0 siblings, 0 replies; 9+ messages in thread From: Cédric Le Goater @ 2023-07-01 9:03 UTC (permalink / raw) To: Nicholas Piggin, Daniel Henrique Barboza, qemu-devel Cc: qemu-ppc, Harsh Prateek Bora, Frederic Barrat >>> When you start building the next PPC PR, I think you can also take >>> this patch : >>> >>> [4/4] target/ppc: Implement core timebase state machine and TFMR >>> https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233612.125879-5-npiggin@gmail.com/ >>> >>> It belongs to the same series. >> >> That doesn't apply cleanly with these 2 patches and it didn't look trivial to >> me. As if there were some code missing. > > Yeah, it actually uses some signals from the nest chiptod patch. > >> If Nick re-send it rebased on top of ppc-next I can queue it. Since it's a >> rebase you can keep the r-b. Thanks, > > I'll see how it goes, it may have to wait for next merge. SMT for > powernv is a little more important since it's more user-facing and it > would be nice to introduce SMT for both pseries and powernv together. Yes. Please resend. I gave the series a good try with an install of 23.04 on a powernv9 machine with 2*2*4 CPUs and running KVM SMP guests with libvirt. It was performing quite well with MTTCG on a 32 CPU ryzen box. No hangs, no crash. This is a great addition. Thanks for it. I'll try VFIO after merge. Cheers, C. > Chiptod for doesn't really do much except step through skiboot init > code, and getting more useful things wired up like TB fault / HMI > injection won't be ready before freeze. > > Thanks, > Nick ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-07-01 9:13 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-06-25 12:03 [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Nicholas Piggin 2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin 2023-06-30 19:36 ` Daniel Henrique Barboza 2023-06-25 12:03 ` [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers Nicholas Piggin 2023-06-30 19:36 ` Daniel Henrique Barboza 2023-06-29 4:58 ` [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Cédric Le Goater 2023-06-30 19:38 ` Daniel Henrique Barboza 2023-07-01 8:38 ` Nicholas Piggin 2023-07-01 9:03 ` Cédric Le Goater
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