From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: dbarboza@ventanamicro.com, alistair23@gmail.com,
richard.henderson@linaro.org
Subject: Re: [PATCH 25/26] target/riscv: remove .instance_post_init
Date: Mon, 12 May 2025 12:33:10 +0200 [thread overview]
Message-ID: <3f774491-87eb-4a88-85b8-ab5e63eadb69@linaro.org> (raw)
In-Reply-To: <20250512095226.93621-26-pbonzini@redhat.com>
Hi Paolo,
On 12/5/25 11:52, Paolo Bonzini wrote:
> Unlike other uses of .instance_post_init, accel_cpu_instance_init()
> *registers* properties, and therefore must be run before
> device_post_init() which sets them to their values from -global.
Does x86_cpu_post_initfn() suffer from the same problem?
> In order to move all registration of properties to .instance_init,
> call accel_cpu_instance_init() at the end of riscv_cpu_init().
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/riscv/cpu.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
next prev parent reply other threads:[~2025-05-12 10:33 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 9:52 [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-05-12 9:52 ` [PATCH 01/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-12 9:52 ` [PATCH 02/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-12 9:52 ` [PATCH 03/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-12 9:52 ` [PATCH 04/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-12 9:52 ` [PATCH 05/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-12 9:52 ` [PATCH 06/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-15 4:51 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 07/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-12 9:52 ` [PATCH 08/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-12 9:52 ` [PATCH 09/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-12 9:52 ` [PATCH 10/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-15 4:51 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 11/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-15 5:00 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 12/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-15 5:28 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 13/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-15 5:29 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 14/26] target/riscv: convert bare " Paolo Bonzini
2025-05-15 5:30 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 15/26] target/riscv: convert dynamic " Paolo Bonzini
2025-05-15 5:31 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 16/26] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-15 5:32 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 17/26] target/riscv: convert ibex " Paolo Bonzini
2025-05-15 5:32 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 18/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-15 5:34 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 19/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-15 5:38 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 20/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-15 5:40 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 21/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-05-15 5:41 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 22/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-15 5:42 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 23/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-15 5:43 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 24/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-15 5:44 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 25/26] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-12 10:33 ` Philippe Mathieu-Daudé [this message]
2025-05-12 10:39 ` Paolo Bonzini
2025-05-15 5:45 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 26/26] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-05-15 6:05 ` [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul Alistair Francis
2025-05-20 6:17 ` Paolo Bonzini
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