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Fri, 02 Aug 2024 06:13:43 -0700 (PDT) Message-ID: <3f7dc025-2589-4ca0-b13c-55b12e11ca61@linaro.org> Date: Fri, 2 Aug 2024 23:13:38 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection To: Ajeet Singh , qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Kyle Evans References: <20240802083423.142365-1-itachis@FreeBSD.org> <20240802083423.142365-7-itachis@FreeBSD.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240802083423.142365-7-itachis@FreeBSD.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/2/24 18:34, Ajeet Singh wrote: > From: Mark Corbin > > Introduced RISC-V specific ELF definitions and hardware capability > detection. > Additionally, a function to retrieve hardware capabilities > ('get_elf_hwcap') is implemented, which returns the common bits set in > each CPU's ISA strings. > > Signed-off-by: Mark Corbin > Signed-off-by: Ajeet Singh > Co-authored-by: Kyle Evans > --- > bsd-user/riscv/target_arch_elf.h | 48 ++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 bsd-user/riscv/target_arch_elf.h > > diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h > new file mode 100644 > index 0000000000..dfb2a3e32e > --- /dev/null > +++ b/bsd-user/riscv/target_arch_elf.h > @@ -0,0 +1,48 @@ > +/* > + * RISC-V ELF definitions > + * > + * Copyright (c) 2019 Mark Corbin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +#ifndef TARGET_ARCH_ELF_H > +#define TARGET_ARCH_ELF_H > + > +#define elf_check_arch(x) ((x) == EM_RISCV) > +#define ELF_START_MMAP 0x80000000 > +#define ELF_ET_DYN_LOAD_ADDR 0x100000 > +#define ELF_CLASS ELFCLASS64 > + > +#define ELF_DATA ELFDATA2LSB > +#define ELF_ARCH EM_RISCV > + > +/* > + * Note: FreeBSD returns things a litle differently than this, but this is as > + * close we have in the emulator. The FreeBSD/riscv64 kernel (in identcpu.c) > + * returns the common bits set in each of the CPUs' ISA strings. Also, unlike > + * linux, we don't mask out specific bits. Given that all user-only cpus are identical, all bits are common. So this really is identical to the freebsd kernel. I think that this comment is more confusing than illuminating. Otherwise, Reviewed-by: Richard Henderson r~