qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 09/14] hw/arm/armsse: Allow boards to specify init-svtor
Date: Mon, 18 Feb 2019 23:01:41 +0100	[thread overview]
Message-ID: <3f81d4c5-8c2f-f8b0-286a-ba732a2794c5@redhat.com> (raw)
In-Reply-To: <20190214125107.22178-10-peter.maydell@linaro.org>

On 2/14/19 1:51 PM, Peter Maydell wrote:
> The Musca boards have DAPLink firmware that sets the initial
> secure VTOR value (the location of the vector table) differently
> depending on the boot mode (from flash, from RAM, etc). Export
> the init-svtor as a QOM property of the ARMSSE object so that
> the board can change it.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  include/hw/arm/armsse.h | 3 +++
>  hw/arm/armsse.c         | 8 ++++----
>  2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index 444605b44dc..84879f40dd8 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -48,6 +48,8 @@
>   *    if necessary.)
>   *  + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
>   *    address of each SRAM bank (and thus the total amount of internal SRAM)
> + *  + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
> + *    (where it expects to load the PC and SP from the vector table on reset)
>   *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
>   *    which are wired to its NVIC lines 32 .. n+32
>   *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
> @@ -204,6 +206,7 @@ typedef struct ARMSSE {
>      uint32_t exp_numirq;
>      uint32_t mainclk_frq;
>      uint32_t sram_addr_width;
> +    uint32_t init_svtor;
>  } ARMSSE;
>  
>  typedef struct ARMSSEInfo ARMSSEInfo;
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 9a8c49547db..3040ea9324e 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -505,11 +505,10 @@ static void armsse_realize(DeviceState *dev, Error **errp)
>           * the INITSVTOR* registers before powering up the CPUs in any case,
>           * so the hardware's default value doesn't matter. QEMU doesn't emulate
>           * the control processor, so instead we behave in the way that the
> -         * firmware does. All boards currently known about have firmware that
> -         * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, like the
> -         * IoTKit default. We can make this more configurable if necessary.
> +         * firmware does. The initial value is configurable by the board code
> +         * to match whatever its firmware does.
>           */
> -        qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000);
> +        qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
>          /*
>           * Start all CPUs except CPU0 powered down. In real hardware it is
>           * a configurable property of the SSE-200 which CPUs start powered up
> @@ -1185,6 +1184,7 @@ static Property armsse_properties[] = {
>      DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
>      DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
>      DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
> +    DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
>      DEFINE_PROP_END_OF_LIST()
>  };
>  
> 

  parent reply	other threads:[~2019-02-18 22:14 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-14 12:50 [Qemu-devel] [PATCH 00/14] Add model of the Arm Musca devboards Peter Maydell
2019-02-14 12:50 ` [Qemu-devel] [PATCH 01/14] hw/arm/armsse: Fix miswiring of expansion IRQs Peter Maydell
2019-02-17 17:49   ` Richard Henderson
2019-02-14 12:50 ` [Qemu-devel] [PATCH 02/14] hw/misc/tz-ppc: Support having unused ports in the middle of the range Peter Maydell
2019-02-17 17:51   ` Richard Henderson
2019-02-14 12:50 ` [Qemu-devel] [PATCH 03/14] hw/timer/pl031: Allow use as an embedded-struct device Peter Maydell
2019-02-17 17:55   ` Richard Henderson
2019-02-18 21:54   ` Philippe Mathieu-Daudé
2019-02-14 12:50 ` [Qemu-devel] [PATCH 04/14] hw/timer/pl031: Convert to using trace events Peter Maydell
2019-02-17 17:56   ` Richard Henderson
2019-02-18 21:58   ` Philippe Mathieu-Daudé
2019-02-14 12:50 ` [Qemu-devel] [PATCH 05/14] hw/char/pl011: Allow use as an embedded-struct device Peter Maydell
2019-02-17 17:57   ` Richard Henderson
2019-02-18 21:59   ` Philippe Mathieu-Daudé
2019-02-14 12:50 ` [Qemu-devel] [PATCH 06/14] hw/char/pl011: Support all interrupt lines Peter Maydell
2019-02-17 18:00   ` Richard Henderson
2019-02-14 12:51 ` [Qemu-devel] [PATCH 07/14] hw/char/pl011: Use '0x' prefix when logging hex numbers Peter Maydell
2019-02-17 18:00   ` Richard Henderson
2019-02-18 22:00   ` Philippe Mathieu-Daudé
2019-02-14 12:51 ` [Qemu-devel] [PATCH 08/14] hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment Peter Maydell
2019-02-17 18:01   ` Richard Henderson
2019-02-14 12:51 ` [Qemu-devel] [PATCH 09/14] hw/arm/armsse: Allow boards to specify init-svtor Peter Maydell
2019-02-17 18:03   ` Richard Henderson
2019-02-18 22:01   ` Philippe Mathieu-Daudé [this message]
2019-02-14 12:51 ` [Qemu-devel] [PATCH 10/14] hw/arm/musca.c: Implement models of the Musca-A and -B1 boards Peter Maydell
2019-02-17 18:09   ` Richard Henderson
2019-02-14 12:51 ` [Qemu-devel] [PATCH 11/14] hw/arm/musca: Add PPCs Peter Maydell
2019-02-17 18:14   ` Richard Henderson
2019-02-17 18:19     ` Richard Henderson
2019-02-14 12:51 ` [Qemu-devel] [PATCH 12/14] hw/arm/musca: Add MPCs Peter Maydell
2019-02-17 18:17   ` Richard Henderson
2019-02-19 12:29   ` Peter Maydell
2019-02-14 12:51 ` [Qemu-devel] [PATCH 13/14] hw/arm/musca: Wire up PL031 RTC Peter Maydell
2019-02-17 18:20   ` Richard Henderson
2019-02-14 12:51 ` [Qemu-devel] [PATCH 14/14] hw/arm/musca: Wire up PL011 UARTs Peter Maydell
2019-02-17 18:20   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3f81d4c5-8c2f-f8b0-286a-ba732a2794c5@redhat.com \
    --to=philmd@redhat.com \
    --cc=patches@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).