Re: [Qemu-devel] [PATCH 01/23] scripts: Add decodetree.py

[Richard Henderson <richard.henderson@linaro.org>]

On 01/11/2018 10:06 AM, Peter Maydell wrote:
> On 18 December 2017 at 17:45, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> To be used to decode ARM SVE, but could be used for any 32-bit RISC.
>> It would need additional work to extend to insn sizes other than 32-bit.
> 
> I guess we could make that extension without requiring all
> existing pattern files to be updated, right?

Sure.  I would expect that to be a command-line option for the script.

> 
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  scripts/decodetree.py | 984 ++++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 984 insertions(+)
>>  create mode 100755 scripts/decodetree.py
> 
> This is rather large for a single patch...

Ok, but... what bits of it are functional without the whole?

> 
>> +# Pattern examples:
>> +#
>> +#   addl_r   010000 ..... ..... .... 0000000 ..... @opr
>> +#   addl_i   010000 ..... ..... .... 0000000 ..... @opi
>> +#
> 
> I think we should insist that a pattern defines all the
> bits (either as constant values or as fields that get
> passed to the decode function). That will help prevent
> accidental under-decoding.

Hmm.  What do you suggest then for bits that the cpu does not decode at all?
This doesn't happen with ARM (I don't think) but it does happen with HPPA, and
probably others.

I suppose I could either wrap it in a field that the translator ignores, or
choose another character besides ".", e.g.

mfia            000000 xxxxx 00000 xxx 10100101 t:5

where bits [21-25] and bits [13-15] really are ignored by hardware.

Thoughts?


r~