From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Luc Michel <luc.michel@amd.com>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
Alistair Francis <alistair@alistair23.me>,
Peter Maydell <peter.maydell@linaro.org>,
Jason Wang <jasowang@redhat.com>,
Francisco Iglesias <francisco.iglesias@amd.com>,
Frederic Konrad <frederic.konrad@amd.com>,
Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Subject: Re: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC
Date: Wed, 18 Oct 2023 11:23:50 +0200 [thread overview]
Message-ID: <404e3e4d-f478-bb50-300e-b41248a1d0cc@linaro.org> (raw)
In-Reply-To: <20231017194422.4124691-12-luc.michel@amd.com>
On 17/10/23 21:44, Luc Michel wrote:
> The CRC was stored in an unsigned variable in gem_receive. Change it for
> a uint32_t to ensure we have the correct variable size here.
>
Fixes: e9f186e514 ("cadence_gem: initial version of device model")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> ---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
next prev parent reply other threads:[~2023-10-18 9:24 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
2023-10-18 6:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers Luc Michel
2023-10-18 10:14 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Luc Michel
2023-10-18 10:15 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG " Luc Michel
2023-10-18 10:18 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG " Luc Michel
2023-10-18 10:20 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Luc Michel
2023-10-18 10:21 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ " Luc Michel
2023-10-18 10:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Luc Michel
2023-10-18 9:22 ` Philippe Mathieu-Daudé
2023-10-17 19:44 ` [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Luc Michel
2023-10-18 10:23 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only Luc Michel
2023-10-18 10:35 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
2023-10-18 9:23 ` Philippe Mathieu-Daudé [this message]
2023-10-18 10:36 ` Boddu, Sai Pavan
2023-10-27 12:16 ` [PATCH 00/11] Various updates for the Cadence GEM model Peter Maydell
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