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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: Re: [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull
Date: Thu, 22 Jun 2023 11:58:25 +0200	[thread overview]
Message-ID: <405f3697-9cc8-3a19-ee79-094e6e130c29@linaro.org> (raw)
In-Reply-To: <20230621121902.1392277-2-richard.henderson@linaro.org>

On 21/6/23 14:18, Richard Henderson wrote:
> We have run out of bits we can use within the CPUTLBEntry comparators,
> as TLB_FLAGS_MASK cannot overlap alignment.
> 
> Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from
> the comparator.  A new TLB_FORCE_SLOW bit is set within the comparator
> as an indication that the slow path must be used.
> 
> Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK.  Since we are out of bits,
> we cannot create a new bit without moving an old one.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   include/exec/cpu-all.h  | 21 +++++++--
>   include/exec/cpu-defs.h |  6 +++
>   accel/tcg/cputlb.c      | 96 ++++++++++++++++++++++++-----------------
>   3 files changed, 80 insertions(+), 43 deletions(-)

Do you mind squashing this for clarity?

-- >8 --
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index c174d5371a..c0f19e5893 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -130,3 +130,3 @@ typedef struct CPUTLBEntryFull {
       */
-    uint8_t slow_flags[3];
+    uint8_t slow_flags[MMU_ACCESS_COUNT];

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4871ad85f0..d07763fdeb 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -86,2 +86,3 @@ typedef enum MMUAccessType {
      MMU_INST_FETCH = 2
+#define MMU_ACCESS_COUNT 3
  } MMUAccessType;
---

Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



  reply	other threads:[~2023-06-22  9:59 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21 12:18 [PATCH v2 0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Richard Henderson
2023-06-21 12:18 ` [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull Richard Henderson
2023-06-22  9:58   ` Philippe Mathieu-Daudé [this message]
2023-06-22 16:05     ` Richard Henderson
2023-06-21 12:18 ` [PATCH v2 2/9] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Richard Henderson
2023-06-22  9:11   ` Philippe Mathieu-Daudé
2023-06-21 12:18 ` [PATCH v2 3/9] accel/tcg: Renumber TLB_DISCARD_WRITE Richard Henderson
2023-06-22  9:09   ` Philippe Mathieu-Daudé
2023-06-21 12:18 ` [PATCH v2 4/9] target/arm: Support 32-byte alignment in pow2_align Richard Henderson
2023-06-22 10:03   ` Philippe Mathieu-Daudé
2023-06-21 12:18 ` [PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit* Richard Henderson
2023-06-21 12:18 ` [PATCH v2 6/9] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Richard Henderson
2023-06-21 12:19 ` [PATCH v2 7/9] accel/tcg: Add TLB_CHECK_ALIGNED Richard Henderson
2023-06-22 10:01   ` Philippe Mathieu-Daudé
2023-06-21 12:19 ` [PATCH v2 8/9] target/arm: Do memory type alignment check when translation disabled Richard Henderson
2023-06-21 12:19 ` [PATCH v2 9/9] target/arm: Do memory type alignment check when translation enabled Richard Henderson

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