* [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
@ 2024-07-04 3:37 ` Bibo Mao
2024-07-15 15:31 ` Philippe Mathieu-Daudé
2024-07-04 3:38 ` [PATCH v2 2/4] hw/intc/loongarch_ipi: Add loongarch ipi support Bibo Mao
` (4 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Bibo Mao @ 2024-07-04 3:37 UTC (permalink / raw)
To: Paolo Bonzini, Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: qemu-devel
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/post_load are used for future kvm child class
2. Interface get_iocsr_as can be used for different architectures,
now MIPS 3A4000 and LoongArch 3A5000 machine use this ip, can inherit
this common class.
3. Interace cpu_by_arch_id is added, by default generic function
cpu_by_arch_id() is used to search vcpu from physical cpuid, it is
generic searching method. Different machine may define other search
methods such binary searching method.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
include/hw/intc/loongson_ipi_common.h | 77 +++++
2 files changed, 471 insertions(+)
create mode 100644 hw/intc/loongson_ipi_common.c
create mode 100644 include/hw/intc/loongson_ipi_common.h
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
new file mode 100644
index 0000000000..3b8b077871
--- /dev/null
+++ b/hw/intc/loongson_ipi_common.c
@@ -0,0 +1,394 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt support
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/sysbus.h"
+#include "hw/intc/loongson_ipi_common.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h"
+#include "exec/memory.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
+ uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ IPICore *s = opaque;
+ uint64_t ret = 0;
+ int index = 0;
+
+ addr &= 0xff;
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ ret = s->status;
+ break;
+ case CORE_EN_OFF:
+ ret = s->en;
+ break;
+ case CORE_SET_OFF:
+ ret = 0;
+ break;
+ case CORE_CLEAR_OFF:
+ ret = 0;
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ ret = s->buf[index];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
+ break;
+ }
+
+ trace_loongson_ipi_read(size, (uint64_t)addr, ret);
+ *data = ret;
+ return MEMTX_OK;
+}
+
+static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
+ uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ LoongsonIPICommonState *ipi = opaque;
+ IPICore *s;
+
+ if (attrs.requester_id >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ s = &ipi->cpu[attrs.requester_id];
+ return loongson_ipi_core_readl(s, addr, data, size, attrs);
+}
+
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val,
+ hwaddr addr, MemTxAttrs attrs)
+{
+ int i, mask = 0, data = 0;
+ AddressSpace *iocsr_as;
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+
+ iocsr_as = NULL;
+ if (licc->get_iocsr_as) {
+ iocsr_as = licc->get_iocsr_as(cpu);
+ }
+
+ if (!iocsr_as) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /*
+ * bit 27-30 is mask for byte writing,
+ * if the mask is 0, we need not to do anything.
+ */
+ if ((val >> 27) & 0xf) {
+ data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
+ for (i = 0; i < 4; i++) {
+ /* get mask for byte writing */
+ if (val & (0x1 << (27 + i))) {
+ mask |= 0xff << (i * 8);
+ }
+ }
+ }
+
+ data &= mask;
+ data |= (val >> 32) & ~mask;
+ address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
+
+ return MEMTX_OK;
+}
+
+static CPUState *get_cpu_by_arch_id(LoongsonIPICommonState *ipi, uint32_t cpuid)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+
+ if (licc->cpu_by_arch_id) {
+ return licc->cpu_by_arch_id(cpuid);
+ }
+
+ return cpu_by_arch_id(cpuid);
+}
+
+static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val,
+ MemTxAttrs attrs)
+{
+ uint32_t cpuid;
+ hwaddr addr;
+ CPUState *cs;
+
+ cpuid = extract32(val, 16, 10);
+ cs = get_cpu_by_arch_id(ipi, cpuid);
+ if (cs == NULL) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /* override requester_id */
+ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
+ attrs.requester_id = cs->cpu_index;
+ return send_ipi_data(ipi, cs, val, addr, attrs);
+}
+
+static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val,
+ MemTxAttrs attrs)
+{
+ uint32_t cpuid;
+ hwaddr addr;
+ CPUState *cs;
+
+ cpuid = extract32(val, 16, 10);
+ cs = get_cpu_by_arch_id(ipi, cpuid);
+ if (cs == NULL) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /* override requester_id */
+ addr = val & 0xffff;
+ attrs.requester_id = cs->cpu_index;
+ return send_ipi_data(ipi, cs, val, addr, attrs);
+}
+
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
+{
+ IPICore *s = opaque;
+ LoongsonIPICommonState *ipi = s->ipi;
+ int index = 0;
+ uint32_t cpuid;
+ uint8_t vector;
+ CPUState *cs;
+
+ addr &= 0xff;
+ trace_loongson_ipi_write(size, (uint64_t)addr, val);
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
+ break;
+ case CORE_EN_OFF:
+ s->en = val;
+ break;
+ case CORE_SET_OFF:
+ s->status |= val;
+ if (s->status != 0 && (s->status & s->en) != 0) {
+ qemu_irq_raise(s->irq);
+ }
+ break;
+ case CORE_CLEAR_OFF:
+ s->status &= ~val;
+ if (s->status == 0 && s->en != 0) {
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ s->buf[index] = val;
+ break;
+ case IOCSR_IPI_SEND:
+ cpuid = extract32(val, 16, 10);
+ /* IPI status vector */
+ vector = extract8(val, 0, 5);
+ cs = get_cpu_by_arch_id(ipi, cpuid);
+ if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+ loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
+ BIT(vector), 4, attrs);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
+ break;
+ }
+
+ return MEMTX_OK;
+}
+
+static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
+{
+ LoongsonIPICommonState *ipi = opaque;
+ IPICore *s;
+
+ if (attrs.requester_id >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ s = &ipi->cpu[attrs.requester_id];
+ return loongson_ipi_core_writel(s, addr, val, size, attrs);
+}
+
+static const MemoryRegionOps loongson_ipi_iocsr_ops = {
+ .read_with_attrs = loongson_ipi_iocsr_readl,
+ .write_with_attrs = loongson_ipi_iocsr_writel,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* mail send and any send only support writeq */
+static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
+{
+ MemTxResult ret = MEMTX_OK;
+ LoongsonIPICommonState *ipi = opaque;
+
+ addr &= 0xfff;
+ switch (addr) {
+ case MAIL_SEND_OFFSET:
+ ret = mail_send(ipi, val, attrs);
+ break;
+ case ANY_SEND_OFFSET:
+ ret = any_send(ipi, val, attrs);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const MemoryRegionOps loongson_ipi64_ops = {
+ .write_with_attrs = loongson_ipi_writeq,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
+{
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ int i;
+
+ if (s->num_cpu == 0) {
+ error_setg(errp, "num-cpu must be at least 1");
+ return;
+ }
+
+ memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
+ &loongson_ipi_iocsr_ops,
+ s, "loongson_ipi_iocsr", 0x48);
+
+ /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */
+ s->ipi_iocsr_mem.disable_reentrancy_guard = true;
+
+ sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
+
+ memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
+ &loongson_ipi64_ops,
+ s, "loongson_ipi64_iocsr", 0x118);
+ sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
+
+ s->cpu = g_new0(IPICore, s->num_cpu);
+ if (s->cpu == NULL) {
+ error_setg(errp, "Memory allocation for IPICore faile");
+ return;
+ }
+
+ for (i = 0; i < s->num_cpu; i++) {
+ s->cpu[i].ipi = s;
+ qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
+ }
+}
+
+static int loongson_ipi_pre_save(void *opaque)
+{
+ LoongsonIPICommonState *s = (LoongsonIPICommonState *)opaque;
+ LoongsonIPICommonClass *c = LOONGSON_IPI_COMMON_GET_CLASS(s);
+
+ if (c->pre_save) {
+ c->pre_save(s);
+ }
+
+ return 0;
+}
+
+static int loongson_ipi_post_load(void *opaque, int version_id)
+{
+ LoongsonIPICommonState *s = (LoongsonIPICommonState *)opaque;
+ LoongsonIPICommonClass *c = LOONGSON_IPI_COMMON_GET_CLASS(s);
+
+ if (c->post_load) {
+ c->post_load(s);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_ipi_core = {
+ .name = "ipi-single",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT32(status, IPICore),
+ VMSTATE_UINT32(en, IPICore),
+ VMSTATE_UINT32(set, IPICore),
+ VMSTATE_UINT32(clear, IPICore),
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_loongson_ipi = {
+ /* Fixed name to keep compatible */
+ .name = "loongson_ipi",
+ .pre_save = loongson_ipi_pre_save,
+ .post_load = loongson_ipi_post_load,
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .fields = (const VMStateField[]) {
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState,
+ num_cpu, vmstate_ipi_core, IPICore),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property ipi_properties[] = {
+ DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = loongson_ipi_common_realize;
+ device_class_set_props(dc, ipi_properties);
+ dc->vmsd = &vmstate_loongson_ipi;
+}
+
+static void loongson_ipi_common_finalize(Object *obj)
+{
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(obj);
+
+ g_free(s->cpu);
+}
+
+static const TypeInfo loongson_ipi_common_info = {
+ .name = TYPE_LOONGSON_IPI_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LoongsonIPICommonState),
+ .class_size = sizeof(LoongsonIPICommonClass),
+ .class_init = loongson_ipi_common_class_init,
+ .instance_finalize = loongson_ipi_common_finalize,
+ .abstract = true,
+};
+
+static void loongson_ipi_common_register_types(void)
+{
+ type_register_static(&loongson_ipi_common_info);
+}
+
+type_init(loongson_ipi_common_register_types)
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
new file mode 100644
index 0000000000..4b75c4572a
--- /dev/null
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGSON_IPI_COMMON_H
+#define HW_LOONGSON_IPI_COMMON_H
+
+#include "hw/sysbus.h"
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF 0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+#define IOCSR_MAIL_SEND 0x48
+#define IOCSR_ANY_SEND 0x158
+
+#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET 0
+#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+
+#define IPI_MBX_NUM 4
+
+#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
+typedef struct LoongsonIPICommonClass LoongsonIPICommonClass;
+typedef struct LoongsonIPICommonState LoongsonIPICommonState;
+DECLARE_OBJ_CHECKERS(LoongsonIPICommonState, LoongsonIPICommonClass,
+ LOONGSON_IPI_COMMON, TYPE_LOONGSON_IPI_COMMON)
+
+typedef struct IPICore {
+ LoongsonIPICommonState *ipi;
+ uint32_t status;
+ uint32_t en;
+ uint32_t set;
+ uint32_t clear;
+ /* 64bit buf divide into 2 32bit buf */
+ uint32_t buf[IPI_MBX_NUM * 2];
+ qemu_irq irq;
+} IPICore;
+
+struct LoongsonIPICommonState {
+ SysBusDevice parent_obj;
+ MemoryRegion ipi_iocsr_mem;
+ MemoryRegion ipi64_iocsr_mem;
+ uint32_t num_cpu;
+ IPICore *cpu;
+};
+
+struct LoongsonIPICommonClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ void (*pre_save)(LoongsonIPICommonState *s);
+ void (*post_load)(LoongsonIPICommonState *s);
+ AddressSpace *(*get_iocsr_as)(CPUState *cpu);
+ CPUState *(*cpu_by_arch_id)(int64_t id);
+};
+
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
+ uint64_t *data,
+ unsigned size, MemTxAttrs attrs);
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs);
+#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class
2024-07-04 3:37 ` [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class Bibo Mao
@ 2024-07-15 15:31 ` Philippe Mathieu-Daudé
2024-07-16 1:11 ` maobibo
0 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-15 15:31 UTC (permalink / raw)
To: Bibo Mao, Paolo Bonzini, Jiaxun Yang, Song Gao; +Cc: qemu-devel
On 4/7/24 05:37, Bibo Mao wrote:
> Loongson ipi common class and instance is created here, it comes
> from file loongson_ipi mostly. For the new added loongson ipi
> common class, there is four interfaces defined here:
> 1. Interfaces pre_save/post_load are used for future kvm child class
> 2. Interface get_iocsr_as can be used for different architectures,
> now MIPS 3A4000 and LoongArch 3A5000 machine use this ip, can inherit
> this common class.
> 3. Interace cpu_by_arch_id is added, by default generic function
> cpu_by_arch_id() is used to search vcpu from physical cpuid, it is
> generic searching method. Different machine may define other search
> methods such binary searching method.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
> include/hw/intc/loongson_ipi_common.h | 77 +++++
> 2 files changed, 471 insertions(+)
> create mode 100644 hw/intc/loongson_ipi_common.c
> create mode 100644 include/hw/intc/loongson_ipi_common.h
> +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
> + uint64_t val,
> + hwaddr addr, MemTxAttrs attrs)
> +{
> + int i, mask = 0, data = 0;
> + AddressSpace *iocsr_as;
> + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
> +
> + iocsr_as = NULL;
> + if (licc->get_iocsr_as) {
> + iocsr_as = licc->get_iocsr_as(cpu);
> + }
> +
> + if (!iocsr_as) {
> + return MEMTX_DECODE_ERROR;
> + }
> +
> + /*
> + * bit 27-30 is mask for byte writing,
> + * if the mask is 0, we need not to do anything.
> + */
> + if ((val >> 27) & 0xf) {
> + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
Adding/removing files make noticing the uncommented changes very hard
(see my v3).
Here you use little-endian instead of host one. This device is L-E only
so this makes sense, but I'd have appreciate at least a comment about
it.
> + for (i = 0; i < 4; i++) {
> + /* get mask for byte writing */
> + if (val & (0x1 << (27 + i))) {
> + mask |= 0xff << (i * 8);
> + }
> + }
> + }
> +
> + data &= mask;
> + data |= (val >> 32) & ~mask;
> + address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
Ditto.
> + return MEMTX_OK;
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class
2024-07-15 15:31 ` Philippe Mathieu-Daudé
@ 2024-07-16 1:11 ` maobibo
0 siblings, 0 replies; 17+ messages in thread
From: maobibo @ 2024-07-16 1:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Paolo Bonzini, Jiaxun Yang, Song Gao
Cc: qemu-devel
On 2024/7/15 下午11:31, Philippe Mathieu-Daudé wrote:
> On 4/7/24 05:37, Bibo Mao wrote:
>> Loongson ipi common class and instance is created here, it comes
>> from file loongson_ipi mostly. For the new added loongson ipi
>> common class, there is four interfaces defined here:
>> 1. Interfaces pre_save/post_load are used for future kvm child class
>> 2. Interface get_iocsr_as can be used for different architectures,
>> now MIPS 3A4000 and LoongArch 3A5000 machine use this ip, can inherit
>> this common class.
>> 3. Interace cpu_by_arch_id is added, by default generic function
>> cpu_by_arch_id() is used to search vcpu from physical cpuid, it is
>> generic searching method. Different machine may define other search
>> methods such binary searching method.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>> hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
>> include/hw/intc/loongson_ipi_common.h | 77 +++++
>> 2 files changed, 471 insertions(+)
>> create mode 100644 hw/intc/loongson_ipi_common.c
>> create mode 100644 include/hw/intc/loongson_ipi_common.h
>
>
>> +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi,
>> CPUState *cpu,
>> + uint64_t val,
>> + hwaddr addr, MemTxAttrs attrs)
>> +{
>> + int i, mask = 0, data = 0;
>> + AddressSpace *iocsr_as;
>> + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
>> +
>> + iocsr_as = NULL;
>> + if (licc->get_iocsr_as) {
>> + iocsr_as = licc->get_iocsr_as(cpu);
>> + }
>> +
>> + if (!iocsr_as) {
>> + return MEMTX_DECODE_ERROR;
>> + }
>> +
>> + /*
>> + * bit 27-30 is mask for byte writing,
>> + * if the mask is 0, we need not to do anything.
>> + */
>> + if ((val >> 27) & 0xf) {
>> + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
>
> Adding/removing files make noticing the uncommented changes very hard
> (see my v3).
>
> Here you use little-endian instead of host one. This device is L-E only
> so this makes sense, but I'd have appreciate at least a comment about
> it.
Good catch, there is compile warning when address_space_ldl() is used,
so address_space_ldl_le() is used to remove compile warning. I will
double check the compile warning issue.
Regard
Bibo Mao
>
>> + for (i = 0; i < 4; i++) {
>> + /* get mask for byte writing */
>> + if (val & (0x1 << (27 + i))) {
>> + mask |= 0xff << (i * 8);
>> + }
>> + }
>> + }
>> +
>> + data &= mask;
>> + data |= (val >> 32) & ~mask;
>> + address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
>
> Ditto.
>
>> + return MEMTX_OK;
>> +}
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 2/4] hw/intc/loongarch_ipi: Add loongarch ipi support
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
2024-07-04 3:37 ` [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class Bibo Mao
@ 2024-07-04 3:38 ` Bibo Mao
2024-07-04 3:38 ` [PATCH v2 3/4] hw/loongarch/virt: Replace loongson ipi with loongarch ipi Bibo Mao
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Bibo Mao @ 2024-07-04 3:38 UTC (permalink / raw)
To: Paolo Bonzini, Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: qemu-devel
Loongarch ipi is added herei, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with kvm mode.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/intc/loongarch_ipi.c | 80 +++++++++++++++++++++++++++++++++
include/hw/intc/loongarch_ipi.h | 33 ++++++++++++++
2 files changed, 113 insertions(+)
create mode 100644 hw/intc/loongarch_ipi.c
create mode 100644 include/hw/intc/loongarch_ipi.h
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 0000000000..91689c35c0
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt support
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/sysbus.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h"
+#include "migration/vmstate.h"
+#include "target/loongarch/cpu.h"
+#include "trace.h"
+
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
+ return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
+
+static int archid_cmp(const void *a, const void *b)
+{
+ CPUArchId *archid_a = (CPUArchId *)a;
+ CPUArchId *archid_b = (CPUArchId *)b;
+
+ return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+ CPUArchId apic_id, *found_cpu;
+
+ apic_id.arch_id = id;
+ found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
+ ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
+ archid_cmp);
+
+ return found_cpu;
+}
+
+static CPUState *get_cpu_by_archid(int64_t arch_id)
+{
+ MachineState *machine = MACHINE(qdev_get_machine());
+ CPUArchId *archid;
+
+ archid = find_cpu_by_archid(machine, arch_id);
+ if (archid) {
+ return CPU(archid->cpu);
+ }
+
+ return NULL;
+}
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+
+ licc->get_iocsr_as = get_iocsr_as;
+ licc->cpu_by_arch_id = get_cpu_by_archid;
+}
+
+static const TypeInfo loongarch_ipi_info = {
+ .name = TYPE_LOONGARCH_IPI,
+ .parent = TYPE_LOONGSON_IPI_COMMON,
+ .instance_size = sizeof(LoongarchIPIState),
+ .class_size = sizeof(LoongarchIPIClass),
+ .class_init = loongarch_ipi_class_init,
+};
+
+static void loongarch_ipi_register_types(void)
+{
+ type_register_static(&loongarch_ipi_info);
+}
+
+type_init(loongarch_ipi_register_types)
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 0000000000..451bbcff5c
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt header files
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
+#include "hw/sysbus.h"
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+typedef struct LoongarchIPIClass LoongarchIPIClass;
+typedef struct LoongarchIPIState LoongarchIPIState;
+DECLARE_OBJ_CHECKERS(LoongarchIPIState, LoongarchIPIClass,
+ LOONGARCH_IPI, TYPE_LOONGARCH_IPI)
+
+struct LoongarchIPIState {
+ LoongsonIPICommonState parent_obj;
+};
+
+struct LoongarchIPIClass {
+ /*< private >*/
+ LoongsonIPICommonClass parent_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+};
+
+#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 3/4] hw/loongarch/virt: Replace loongson ipi with loongarch ipi
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
2024-07-04 3:37 ` [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class Bibo Mao
2024-07-04 3:38 ` [PATCH v2 2/4] hw/intc/loongarch_ipi: Add loongarch ipi support Bibo Mao
@ 2024-07-04 3:38 ` Bibo Mao
2024-07-04 3:38 ` [PATCH v2 4/4] hw/intc/loongson_ipi: reconstruct driver inherit from common class Bibo Mao
` (2 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Bibo Mao @ 2024-07-04 3:38 UTC (permalink / raw)
To: Paolo Bonzini, Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: qemu-devel
Loongarch ipi inherits from class LoongsonIPICommonClass, and it only
contains Loongarch 3A5000 virt machine specific interfaces, rather than
mix different machine implementations together.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/intc/Kconfig | 3 +++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 2 +-
hw/loongarch/virt.c | 4 ++--
include/hw/loongarch/virt.h | 1 -
5 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 58b6d3a710..870f537236 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -90,6 +90,9 @@ config M68K_IRQC
config LOONGSON_IPI
bool
+config LOONGARCH_IPI
+ bool
+
config LOONGARCH_PCH_PIC
bool
select UNIMP
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index afd1aa51ee..b7fce2f375 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -70,6 +70,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c', 'loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 90a0dba9d5..830cfef72d 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -11,7 +11,7 @@ config LOONGARCH_VIRT
select SERIAL
select VIRTIO_PCI
select PLATFORM_BUS
- select LOONGSON_IPI
+ select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
select LOONGARCH_EXTIOI
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 8be2d2ff6a..6bef2f1165 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -23,7 +23,7 @@
#include "net/net.h"
#include "hw/loader.h"
#include "elf.h"
-#include "hw/intc/loongson_ipi.h"
+#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
@@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
*/
/* Create IPI device */
- ipi = qdev_new(TYPE_LOONGSON_IPI);
+ ipi = qdev_new(TYPE_LOONGARCH_IPI);
qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 8fdfacf268..91216418c8 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -11,7 +11,6 @@
#include "target/loongarch/cpu.h"
#include "hw/boards.h"
#include "qemu/queue.h"
-#include "hw/intc/loongson_ipi.h"
#include "hw/block/flash.h"
#include "hw/loongarch/boot.h"
--
2.39.3
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 4/4] hw/intc/loongson_ipi: reconstruct driver inherit from common class
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
` (2 preceding siblings ...)
2024-07-04 3:38 ` [PATCH v2 3/4] hw/loongarch/virt: Replace loongson ipi with loongarch ipi Bibo Mao
@ 2024-07-04 3:38 ` Bibo Mao
2024-07-09 12:04 ` [PATCH v2 0/4] Reconstruct loongson ipi driver maobibo
2024-07-15 15:17 ` Philippe Mathieu-Daudé
5 siblings, 0 replies; 17+ messages in thread
From: Bibo Mao @ 2024-07-04 3:38 UTC (permalink / raw)
To: Paolo Bonzini, Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: qemu-devel
Like loongarch ipi, reconstruct this driver by inheriting class
LoongsonIPICommonClass. Add extra function loongson_ipi_realize()
to implement mmio memory region.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/intc/loongson_ipi.c | 330 +++------------------------------
hw/intc/meson.build | 2 +-
include/hw/intc/loongson_ipi.h | 54 ++----
3 files changed, 41 insertions(+), 345 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e6a7142480..42c3cff9ac 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -15,213 +15,16 @@
#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
-#ifdef TARGET_LOONGARCH64
-#include "target/loongarch/cpu.h"
-#endif
-#ifdef TARGET_MIPS
#include "target/mips/cpu.h"
-#endif
#include "trace.h"
-static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
+static AddressSpace *get_iocsr_as(CPUState *cpu)
{
- IPICore *s = opaque;
- uint64_t ret = 0;
- int index = 0;
-
- addr &= 0xff;
- switch (addr) {
- case CORE_STATUS_OFF:
- ret = s->status;
- break;
- case CORE_EN_OFF:
- ret = s->en;
- break;
- case CORE_SET_OFF:
- ret = 0;
- break;
- case CORE_CLEAR_OFF:
- ret = 0;
- break;
- case CORE_BUF_20 ... CORE_BUF_38 + 4:
- index = (addr - CORE_BUF_20) >> 2;
- ret = s->buf[index];
- break;
- default:
- qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
- break;
- }
-
- trace_loongson_ipi_read(size, (uint64_t)addr, ret);
- *data = ret;
- return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
-{
- LoongsonIPI *ipi = opaque;
- IPICore *s;
-
- if (attrs.requester_id >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
-
- s = &ipi->cpu[attrs.requester_id];
- return loongson_ipi_core_readl(s, addr, data, size, attrs);
-}
-
-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
-{
-#ifdef TARGET_LOONGARCH64
- return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
-#endif
-#ifdef TARGET_MIPS
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
return &MIPS_CPU(cpu)->env.iocsr.as;
}
-#endif
- return NULL;
-}
-
-static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
-{
- int i, mask = 0, data = 0;
- AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
-
- if (!iocsr_as) {
- return MEMTX_DECODE_ERROR;
- }
-
- /*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
- if ((val >> 27) & 0xf) {
- data = address_space_ldl(iocsr_as, addr, attrs, NULL);
- for (i = 0; i < 4; i++) {
- /* get mask for byte writing */
- if (val & (0x1 << (27 + i))) {
- mask |= 0xff << (i * 8);
- }
- }
- }
-
- data &= mask;
- data |= (val >> 32) & ~mask;
- address_space_stl(iocsr_as, addr, data, attrs, NULL);
-
- return MEMTX_OK;
-}
-
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
-{
- uint32_t cpuid;
- hwaddr addr;
- CPUState *cs;
-
- cpuid = extract32(val, 16, 10);
- cs = cpu_by_arch_id(cpuid);
- if (cs == NULL) {
- return MEMTX_DECODE_ERROR;
- }
-
- /* override requester_id */
- addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
- attrs.requester_id = cs->cpu_index;
- return send_ipi_data(cs, val, addr, attrs);
-}
-
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
-{
- uint32_t cpuid;
- hwaddr addr;
- CPUState *cs;
-
- cpuid = extract32(val, 16, 10);
- cs = cpu_by_arch_id(cpuid);
- if (cs == NULL) {
- return MEMTX_DECODE_ERROR;
- }
-
- /* override requester_id */
- addr = val & 0xffff;
- attrs.requester_id = cs->cpu_index;
- return send_ipi_data(cs, val, addr, attrs);
-}
-
-static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
- uint64_t val, unsigned size,
- MemTxAttrs attrs)
-{
- IPICore *s = opaque;
- LoongsonIPI *ipi = s->ipi;
- int index = 0;
- uint32_t cpuid;
- uint8_t vector;
- CPUState *cs;
-
- addr &= 0xff;
- trace_loongson_ipi_write(size, (uint64_t)addr, val);
- switch (addr) {
- case CORE_STATUS_OFF:
- qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
- break;
- case CORE_EN_OFF:
- s->en = val;
- break;
- case CORE_SET_OFF:
- s->status |= val;
- if (s->status != 0 && (s->status & s->en) != 0) {
- qemu_irq_raise(s->irq);
- }
- break;
- case CORE_CLEAR_OFF:
- s->status &= ~val;
- if (s->status == 0 && s->en != 0) {
- qemu_irq_lower(s->irq);
- }
- break;
- case CORE_BUF_20 ... CORE_BUF_38 + 4:
- index = (addr - CORE_BUF_20) >> 2;
- s->buf[index] = val;
- break;
- case IOCSR_IPI_SEND:
- cpuid = extract32(val, 16, 10);
- /* IPI status vector */
- vector = extract8(val, 0, 5);
- cs = cpu_by_arch_id(cpuid);
- if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
- loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
- BIT(vector), 4, attrs);
- break;
- default:
- qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
- break;
- }
- return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
- uint64_t val, unsigned size,
- MemTxAttrs attrs)
-{
- LoongsonIPI *ipi = opaque;
- IPICore *s;
-
- if (attrs.requester_id >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
-
- s = &ipi->cpu[attrs.requester_id];
- return loongson_ipi_core_writel(s, addr, val, size, attrs);
+ return NULL;
}
static const MemoryRegionOps loongson_ipi_core_ops = {
@@ -234,139 +37,54 @@ static const MemoryRegionOps loongson_ipi_core_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static const MemoryRegionOps loongson_ipi_iocsr_ops = {
- .read_with_attrs = loongson_ipi_iocsr_readl,
- .write_with_attrs = loongson_ipi_iocsr_writel,
- .impl.min_access_size = 4,
- .impl.max_access_size = 4,
- .valid.min_access_size = 4,
- .valid.max_access_size = 8,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-/* mail send and any send only support writeq */
-static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
- MemTxResult ret = MEMTX_OK;
-
- addr &= 0xfff;
- switch (addr) {
- case MAIL_SEND_OFFSET:
- ret = mail_send(val, attrs);
- break;
- case ANY_SEND_OFFSET:
- ret = any_send(val, attrs);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static const MemoryRegionOps loongson_ipi64_ops = {
- .write_with_attrs = loongson_ipi_writeq,
- .impl.min_access_size = 8,
- .impl.max_access_size = 8,
- .valid.min_access_size = 8,
- .valid.max_access_size = 8,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
- LoongsonIPI *s = LOONGSON_IPI(dev);
+ LoongsonIPIState *s = LOONGSON_IPI(dev);
+ LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(s);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ Error *local_err = NULL;
int i;
- if (s->num_cpu == 0) {
- error_setg(errp, "num-cpu must be at least 1");
- return;
- }
-
- memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
- &loongson_ipi_iocsr_ops,
- s, "loongson_ipi_iocsr", 0x48);
-
- /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */
- s->ipi_iocsr_mem.disable_reentrancy_guard = true;
-
- sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
-
- memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
- &loongson_ipi64_ops,
- s, "loongson_ipi64_iocsr", 0x118);
- sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
-
- s->cpu = g_new0(IPICore, s->num_cpu);
- if (s->cpu == NULL) {
- error_setg(errp, "Memory allocation for IPICore faile");
+ lic->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
return;
}
- for (i = 0; i < s->num_cpu; i++) {
- s->cpu[i].ipi = s;
- s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
+ s->ipi_mmio_mem = g_new0(MemoryRegion, s->parent_obj.num_cpu);
+ for (i = 0; i < s->parent_obj.num_cpu; i++) {
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
- memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
- &loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
- sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
-
- qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
+ memory_region_init_io(s->ipi_mmio_mem + i, OBJECT(dev),
+ &loongson_ipi_core_ops, &s->parent_obj.cpu[i],
+ name, 0x48);
+ sysbus_init_mmio(sbd, s->ipi_mmio_mem + i);
}
}
-static const VMStateDescription vmstate_ipi_core = {
- .name = "ipi-single",
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (const VMStateField[]) {
- VMSTATE_UINT32(status, IPICore),
- VMSTATE_UINT32(en, IPICore),
- VMSTATE_UINT32(set, IPICore),
- VMSTATE_UINT32(clear, IPICore),
- VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static const VMStateDescription vmstate_loongson_ipi = {
- .name = TYPE_LOONGSON_IPI,
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (const VMStateField[]) {
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
- vmstate_ipi_core, IPICore),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static Property ipi_properties[] = {
- DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+ LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
- dc->realize = loongson_ipi_realize;
- device_class_set_props(dc, ipi_properties);
- dc->vmsd = &vmstate_loongson_ipi;
+ device_class_set_parent_realize(dc, loongson_ipi_realize,
+ &lic->parent_realize);
+ licc->get_iocsr_as = get_iocsr_as;
}
static void loongson_ipi_finalize(Object *obj)
{
- LoongsonIPI *s = LOONGSON_IPI(obj);
+ LoongsonIPIState *s = LOONGSON_IPI(obj);
- g_free(s->cpu);
+ g_free(s->ipi_mmio_mem);
}
static const TypeInfo loongson_ipi_info = {
.name = TYPE_LOONGSON_IPI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(LoongsonIPI),
+ .parent = TYPE_LOONGSON_IPI_COMMON,
+ .instance_size = sizeof(LoongsonIPIState),
+ .class_size = sizeof(LoongsonIPIClass),
.class_init = loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
};
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index b7fce2f375..81b72d57bc 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -69,7 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
-specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c', 'loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c', 'loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 3f795edbf3..acf2b9d9a6 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -8,49 +8,27 @@
#ifndef HW_LOONGSON_IPI_H
#define HW_LOONGSON_IPI_H
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-/* Mainy used by iocsr read and write */
-#define SMP_IPI_MAILBOX 0x1000ULL
-#define CORE_STATUS_OFF 0x0
-#define CORE_EN_OFF 0x4
-#define CORE_SET_OFF 0x8
-#define CORE_CLEAR_OFF 0xc
-#define CORE_BUF_20 0x20
-#define CORE_BUF_28 0x28
-#define CORE_BUF_30 0x30
-#define CORE_BUF_38 0x38
-#define IOCSR_IPI_SEND 0x40
-#define IOCSR_MAIL_SEND 0x48
-#define IOCSR_ANY_SEND 0x158
+#define TYPE_LOONGSON_IPI "loongson_ipi"
+typedef struct LoongsonIPIClass LoongsonIPIClass;
+typedef struct LoongsonIPIState LoongsonIPIState;
+DECLARE_OBJ_CHECKERS(LoongsonIPIState, LoongsonIPIClass,
+ LOONGSON_IPI, TYPE_LOONGSON_IPI)
-#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
-#define MAIL_SEND_OFFSET 0
-#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
-
-#define IPI_MBX_NUM 4
-
-#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
-
-typedef struct IPICore {
- LoongsonIPI *ipi;
+struct LoongsonIPIState {
+ LoongsonIPICommonState parent_obj;
MemoryRegion *ipi_mmio_mem;
- uint32_t status;
- uint32_t en;
- uint32_t set;
- uint32_t clear;
- /* 64bit buf divide into 2 32bit buf */
- uint32_t buf[IPI_MBX_NUM * 2];
- qemu_irq irq;
-} IPICore;
+};
+
+struct LoongsonIPIClass {
+ /*< private >*/
+ LoongsonIPICommonClass parent_class;
+ /*< public >*/
-struct LoongsonIPI {
- SysBusDevice parent_obj;
- MemoryRegion ipi_iocsr_mem;
- MemoryRegion ipi64_iocsr_mem;
- uint32_t num_cpu;
- IPICore *cpu;
+ DeviceRealize parent_realize;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
` (3 preceding siblings ...)
2024-07-04 3:38 ` [PATCH v2 4/4] hw/intc/loongson_ipi: reconstruct driver inherit from common class Bibo Mao
@ 2024-07-09 12:04 ` maobibo
2024-07-10 4:00 ` Jiaxun Yang
2024-07-15 15:17 ` Philippe Mathieu-Daudé
5 siblings, 1 reply; 17+ messages in thread
From: maobibo @ 2024-07-09 12:04 UTC (permalink / raw)
To: Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: Paolo Bonzini, qemu-devel
Hi Philippe/Jiaxun,
Could you do me a favor giving a review about this patch?
Regards
Bibo Mao
On 2024/7/4 上午11:37, Bibo Mao wrote:
> Now loongson ipi and loongarch ipi share the same code with different
> macro, loongson ipi has its separate function such mmio region,
> loongarch ipi has other requirement such as irqchip in kernel.
>
> Interrupt irqchip has strong relationship with architecture, since
> it sends irq to vcpu and interfaces to get irqchip register is also
> architecture specific.
>
> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
> is added, it comes from loongson ipi mostly. And it defined four abstract
> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000 machine,
> also can be used for 3A5000 irqchip in kernel mode soon.
>
> Also Loongarch ipi and loongson ipi device are added here, it inherits
> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
> loongson ipi device only passes to compile and make check, it is not
> tested.
>
> Bibo Mao (4):
> hw/intc/loongson_ipi_common: Add loongson ipi common class
> hw/intc/loongarch_ipi: Add loongarch ipi support
> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>
> hw/intc/Kconfig | 3 +
> hw/intc/loongarch_ipi.c | 80 ++++++
> hw/intc/loongson_ipi.c | 330 ++-------------------
> hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
> hw/intc/meson.build | 3 +-
> hw/loongarch/Kconfig | 2 +-
> hw/loongarch/virt.c | 4 +-
> include/hw/intc/loongarch_ipi.h | 33 +++
> include/hw/intc/loongson_ipi.h | 54 ++--
> include/hw/intc/loongson_ipi_common.h | 77 +++++
> include/hw/loongarch/virt.h | 1 -
> 11 files changed, 632 insertions(+), 349 deletions(-)
> create mode 100644 hw/intc/loongarch_ipi.c
> create mode 100644 hw/intc/loongson_ipi_common.c
> create mode 100644 include/hw/intc/loongarch_ipi.h
> create mode 100644 include/hw/intc/loongson_ipi_common.h
>
>
> base-commit: 6746482d12da3b6e4d3cdf06481a0027a797f719
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-09 12:04 ` [PATCH v2 0/4] Reconstruct loongson ipi driver maobibo
@ 2024-07-10 4:00 ` Jiaxun Yang
2024-07-10 6:08 ` maobibo
0 siblings, 1 reply; 17+ messages in thread
From: Jiaxun Yang @ 2024-07-10 4:00 UTC (permalink / raw)
To: Bibo Mao, Philippe Mathieu-Daudé, Song Gao; +Cc: Paolo Bonzini, QEMU devel
在2024年7月9日七月 下午8:04，maobibo写道：
> Hi Philippe/Jiaxun,
>
> Could you do me a favor giving a review about this patch?
Hi Bibo,
I’m currently traveling, will test and review next week.
I’m not really convinced to give a R-b but I’m fine with a T-b.
Thanks
>
> Regards
> Bibo Mao
>
> On 2024/7/4 上午11:37, Bibo Mao wrote:
>> Now loongson ipi and loongarch ipi share the same code with different
>> macro, loongson ipi has its separate function such mmio region,
>> loongarch ipi has other requirement such as irqchip in kernel.
>>
>> Interrupt irqchip has strong relationship with architecture, since
>> it sends irq to vcpu and interfaces to get irqchip register is also
>> architecture specific.
>>
>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>> is added, it comes from loongson ipi mostly. And it defined four abstract
>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000 machine,
>> also can be used for 3A5000 irqchip in kernel mode soon.
>>
>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>> loongson ipi device only passes to compile and make check, it is not
>> tested.
>>
>> Bibo Mao (4):
>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>> hw/intc/loongarch_ipi: Add loongarch ipi support
>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>
>> hw/intc/Kconfig | 3 +
>> hw/intc/loongarch_ipi.c | 80 ++++++
>> hw/intc/loongson_ipi.c | 330 ++-------------------
>> hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
>> hw/intc/meson.build | 3 +-
>> hw/loongarch/Kconfig | 2 +-
>> hw/loongarch/virt.c | 4 +-
>> include/hw/intc/loongarch_ipi.h | 33 +++
>> include/hw/intc/loongson_ipi.h | 54 ++--
>> include/hw/intc/loongson_ipi_common.h | 77 +++++
>> include/hw/loongarch/virt.h | 1 -
>> 11 files changed, 632 insertions(+), 349 deletions(-)
>> create mode 100644 hw/intc/loongarch_ipi.c
>> create mode 100644 hw/intc/loongson_ipi_common.c
>> create mode 100644 include/hw/intc/loongarch_ipi.h
>> create mode 100644 include/hw/intc/loongson_ipi_common.h
>>
>>
>> base-commit: 6746482d12da3b6e4d3cdf06481a0027a797f719
>>
--
- Jiaxun
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-10 4:00 ` Jiaxun Yang
@ 2024-07-10 6:08 ` maobibo
0 siblings, 0 replies; 17+ messages in thread
From: maobibo @ 2024-07-10 6:08 UTC (permalink / raw)
To: Jiaxun Yang, Philippe Mathieu-Daudé, Song Gao
Cc: Paolo Bonzini, QEMU devel
On 2024/7/10 下午12:00, Jiaxun Yang wrote:
>
>
> 在2024年7月9日七月 下午8:04，maobibo写道：
>> Hi Philippe/Jiaxun,
>>
>> Could you do me a favor giving a review about this patch?
>
> Hi Bibo,
>
> I’m currently traveling, will test and review next week.
>
> I’m not really convinced to give a R-b but I’m fine with a T-b.
That is ok for me, have a good time.
Regards
Bibo Mao
>
> Thanks
>
>>
>> Regards
>> Bibo Mao
>>
>> On 2024/7/4 上午11:37, Bibo Mao wrote:
>>> Now loongson ipi and loongarch ipi share the same code with different
>>> macro, loongson ipi has its separate function such mmio region,
>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>
>>> Interrupt irqchip has strong relationship with architecture, since
>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>> architecture specific.
>>>
>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>> is added, it comes from loongson ipi mostly. And it defined four abstract
>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000 machine,
>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>
>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>> loongson ipi device only passes to compile and make check, it is not
>>> tested.
>>>
>>> Bibo Mao (4):
>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>>
>>> hw/intc/Kconfig | 3 +
>>> hw/intc/loongarch_ipi.c | 80 ++++++
>>> hw/intc/loongson_ipi.c | 330 ++-------------------
>>> hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++
>>> hw/intc/meson.build | 3 +-
>>> hw/loongarch/Kconfig | 2 +-
>>> hw/loongarch/virt.c | 4 +-
>>> include/hw/intc/loongarch_ipi.h | 33 +++
>>> include/hw/intc/loongson_ipi.h | 54 ++--
>>> include/hw/intc/loongson_ipi_common.h | 77 +++++
>>> include/hw/loongarch/virt.h | 1 -
>>> 11 files changed, 632 insertions(+), 349 deletions(-)
>>> create mode 100644 hw/intc/loongarch_ipi.c
>>> create mode 100644 hw/intc/loongson_ipi_common.c
>>> create mode 100644 include/hw/intc/loongarch_ipi.h
>>> create mode 100644 include/hw/intc/loongson_ipi_common.h
>>>
>>>
>>> base-commit: 6746482d12da3b6e4d3cdf06481a0027a797f719
>>>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-04 3:37 [PATCH v2 0/4] Reconstruct loongson ipi driver Bibo Mao
` (4 preceding siblings ...)
2024-07-09 12:04 ` [PATCH v2 0/4] Reconstruct loongson ipi driver maobibo
@ 2024-07-15 15:17 ` Philippe Mathieu-Daudé
2024-07-16 1:04 ` maobibo
5 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-15 15:17 UTC (permalink / raw)
To: Bibo Mao, Paolo Bonzini, Jiaxun Yang, Song Gao; +Cc: qemu-devel
On 4/7/24 05:37, Bibo Mao wrote:
> Now loongson ipi and loongarch ipi share the same code with different
> macro, loongson ipi has its separate function such mmio region,
> loongarch ipi has other requirement such as irqchip in kernel.
>
> Interrupt irqchip has strong relationship with architecture, since
> it sends irq to vcpu and interfaces to get irqchip register is also
> architecture specific.
>
> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
> is added, it comes from loongson ipi mostly. And it defined four abstract
> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000 machine,
> also can be used for 3A5000 irqchip in kernel mode soon.
>
> Also Loongarch ipi and loongson ipi device are added here, it inherits
> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
> loongson ipi device only passes to compile and make check, it is not
> tested.
>
> Bibo Mao (4):
> hw/intc/loongson_ipi_common: Add loongson ipi common class
> hw/intc/loongarch_ipi: Add loongarch ipi support
> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
> hw/intc/loongson_ipi: reconstruct driver inherit from common class
I'll try to respin a clearer v3.
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-15 15:17 ` Philippe Mathieu-Daudé
@ 2024-07-16 1:04 ` maobibo
2024-07-16 1:29 ` maobibo
0 siblings, 1 reply; 17+ messages in thread
From: maobibo @ 2024-07-16 1:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Paolo Bonzini, Jiaxun Yang, Song Gao
Cc: qemu-devel
On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
> On 4/7/24 05:37, Bibo Mao wrote:
>> Now loongson ipi and loongarch ipi share the same code with different
>> macro, loongson ipi has its separate function such mmio region,
>> loongarch ipi has other requirement such as irqchip in kernel.
>>
>> Interrupt irqchip has strong relationship with architecture, since
>> it sends irq to vcpu and interfaces to get irqchip register is also
>> architecture specific.
>>
>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>> is added, it comes from loongson ipi mostly. And it defined four abstract
>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>> machine,
>> also can be used for 3A5000 irqchip in kernel mode soon.
>>
>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>> loongson ipi device only passes to compile and make check, it is not
>> tested.
>>
>> Bibo Mao (4):
>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>> hw/intc/loongarch_ipi: Add loongarch ipi support
>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>
> I'll try to respin a clearer v3.
I am ok with it since it solve the problem, and it is suitable for 9.1
release. Only that in the long time we hope that intc emulation driver
has common base class + tcg/kvm driver, similar with other architecture.
Regards
Bibo mao
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-16 1:04 ` maobibo
@ 2024-07-16 1:29 ` maobibo
2024-07-16 6:40 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 17+ messages in thread
From: maobibo @ 2024-07-16 1:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Paolo Bonzini, Jiaxun Yang, Song Gao
Cc: qemu-devel
On 2024/7/16 上午9:04, maobibo wrote:
>
>
> On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
>> On 4/7/24 05:37, Bibo Mao wrote:
>>> Now loongson ipi and loongarch ipi share the same code with different
>>> macro, loongson ipi has its separate function such mmio region,
>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>
>>> Interrupt irqchip has strong relationship with architecture, since
>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>> architecture specific.
>>>
>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>> is added, it comes from loongson ipi mostly. And it defined four
>>> abstract
>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>>> machine,
>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>
>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>> loongson ipi device only passes to compile and make check, it is not
>>> tested.
>>>
>>> Bibo Mao (4):
>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>
>> I'll try to respin a clearer v3.
> I am ok with it since it solve the problem, and it is suitable for 9.1
> release. Only that in the long time we hope that intc emulation driver
> has common base class + tcg/kvm driver, similar with other architecture.
>
Sorry for the confusion, I had thought it was another topic.
Thanks for pointing out the problem and welcome the v3 version.
Regards
Bibo Mao
> Regards
> Bibo mao
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-16 1:29 ` maobibo
@ 2024-07-16 6:40 ` Philippe Mathieu-Daudé
2024-07-17 9:22 ` maobibo
0 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-16 6:40 UTC (permalink / raw)
To: maobibo, Paolo Bonzini, Jiaxun Yang, Song Gao; +Cc: qemu-devel
On 16/7/24 03:29, maobibo wrote:
>
>
> On 2024/7/16 上午9:04, maobibo wrote:
>>
>>
>> On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
>>> On 4/7/24 05:37, Bibo Mao wrote:
>>>> Now loongson ipi and loongarch ipi share the same code with different
>>>> macro, loongson ipi has its separate function such mmio region,
>>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>>
>>>> Interrupt irqchip has strong relationship with architecture, since
>>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>>> architecture specific.
>>>>
>>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>>> is added, it comes from loongson ipi mostly. And it defined four
>>>> abstract
>>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>>>> machine,
>>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>>
>>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>>> loongson ipi device only passes to compile and make check, it is not
>>>> tested.
>>>>
>>>> Bibo Mao (4):
>>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>>
>>> I'll try to respin a clearer v3.
>> I am ok with it since it solve the problem, and it is suitable for 9.1
>> release. Only that in the long time we hope that intc emulation driver
>> has common base class + tcg/kvm driver, similar with other architecture.
>>
> Sorry for the confusion, I had thought it was another topic.
>
> Thanks for pointing out the problem and welcome the v3 version.
Please do not post v3, let me post it.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-16 6:40 ` Philippe Mathieu-Daudé
@ 2024-07-17 9:22 ` maobibo
2024-07-17 11:53 ` Jiaxun Yang
0 siblings, 1 reply; 17+ messages in thread
From: maobibo @ 2024-07-17 9:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Paolo Bonzini, Jiaxun Yang, Song Gao
Cc: qemu-devel
On 2024/7/16 下午2:40, Philippe Mathieu-Daudé wrote:
> On 16/7/24 03:29, maobibo wrote:
>>
>>
>> On 2024/7/16 上午9:04, maobibo wrote:
>>>
>>>
>>> On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
>>>> On 4/7/24 05:37, Bibo Mao wrote:
>>>>> Now loongson ipi and loongarch ipi share the same code with different
>>>>> macro, loongson ipi has its separate function such mmio region,
>>>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>>>
>>>>> Interrupt irqchip has strong relationship with architecture, since
>>>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>>>> architecture specific.
>>>>>
>>>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>>>> is added, it comes from loongson ipi mostly. And it defined four
>>>>> abstract
>>>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>>>>> machine,
>>>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>>>
>>>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>>>> loongson ipi device only passes to compile and make check, it is not
>>>>> tested.
>>>>>
>>>>> Bibo Mao (4):
>>>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>>>
>>>> I'll try to respin a clearer v3.
>>> I am ok with it since it solve the problem, and it is suitable for
>>> 9.1 release. Only that in the long time we hope that intc emulation
>>> driver has common base class + tcg/kvm driver, similar with other
>>> architecture.
>>>
>> Sorry for the confusion, I had thought it was another topic.
>>
>> Thanks for pointing out the problem and welcome the v3 version.
>
> Please do not post v3, let me post it.
Hi Philippe,
QEMU 9.1 is coming to soft frozen stage, do you have enough time working
on it? Is it ok to use bugfix patch for 9.1 release version?
https://lore.kernel.org/all/20240627125819.62779-2-philmd@linaro.org/
After 9.1 is released, there will be enough time for patch v3.
Regards
Bibo, Mao
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-17 9:22 ` maobibo
@ 2024-07-17 11:53 ` Jiaxun Yang
2024-07-17 21:41 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 17+ messages in thread
From: Jiaxun Yang @ 2024-07-17 11:53 UTC (permalink / raw)
To: Bibo Mao, Philippe Mathieu-Daudé, Paolo Bonzini, Song Gao; +Cc: QEMU devel
在2024年7月17日七月 下午5:22，maobibo写道：
> On 2024/7/16 下午2:40, Philippe Mathieu-Daudé wrote:
>> On 16/7/24 03:29, maobibo wrote:
>>>
>>>
>>> On 2024/7/16 上午9:04, maobibo wrote:
>>>>
>>>>
>>>> On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
>>>>> On 4/7/24 05:37, Bibo Mao wrote:
>>>>>> Now loongson ipi and loongarch ipi share the same code with different
>>>>>> macro, loongson ipi has its separate function such mmio region,
>>>>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>>>>
>>>>>> Interrupt irqchip has strong relationship with architecture, since
>>>>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>>>>> architecture specific.
>>>>>>
>>>>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>>>>> is added, it comes from loongson ipi mostly. And it defined four
>>>>>> abstract
>>>>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>>>>>> machine,
>>>>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>>>>
>>>>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>>>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>>>>> loongson ipi device only passes to compile and make check, it is not
>>>>>> tested.
>>>>>>
>>>>>> Bibo Mao (4):
>>>>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>>>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>>>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>>>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>>>>
>>>>> I'll try to respin a clearer v3.
>>>> I am ok with it since it solve the problem, and it is suitable for
>>>> 9.1 release. Only that in the long time we hope that intc emulation
>>>> driver has common base class + tcg/kvm driver, similar with other
>>>> architecture.
>>>>
>>> Sorry for the confusion, I had thought it was another topic.
>>>
>>> Thanks for pointing out the problem and welcome the v3 version.
>>
>> Please do not post v3, let me post it.
> Hi Philippe,
>
> QEMU 9.1 is coming to soft frozen stage, do you have enough time working
> on it? Is it ok to use bugfix patch for 9.1 release version?
Bug fix is always qualified between soft freeze and release.
I tested the series for MIPS yesterday and can confirm it do work.
Will give my tags on v3.
Thanks
> https://lore.kernel.org/all/20240627125819.62779-2-philmd@linaro.org/
>
> After 9.1 is released, there will be enough time for patch v3.
>
> Regards
> Bibo, Mao
--
- Jiaxun
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/4] Reconstruct loongson ipi driver
2024-07-17 11:53 ` Jiaxun Yang
@ 2024-07-17 21:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-17 21:41 UTC (permalink / raw)
To: Jiaxun Yang, Bibo Mao, Paolo Bonzini, Song Gao; +Cc: QEMU devel
On 17/7/24 13:53, Jiaxun Yang wrote:
>
>
> 在2024年7月17日七月 下午5:22，maobibo写道：
>> On 2024/7/16 下午2:40, Philippe Mathieu-Daudé wrote:
>>> On 16/7/24 03:29, maobibo wrote:
>>>>
>>>>
>>>> On 2024/7/16 上午9:04, maobibo wrote:
>>>>>
>>>>>
>>>>> On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote:
>>>>>> On 4/7/24 05:37, Bibo Mao wrote:
>>>>>>> Now loongson ipi and loongarch ipi share the same code with different
>>>>>>> macro, loongson ipi has its separate function such mmio region,
>>>>>>> loongarch ipi has other requirement such as irqchip in kernel.
>>>>>>>
>>>>>>> Interrupt irqchip has strong relationship with architecture, since
>>>>>>> it sends irq to vcpu and interfaces to get irqchip register is also
>>>>>>> architecture specific.
>>>>>>>
>>>>>>> Here like other architectures, base class TYPE_LOONGSON_IPI_COMMON
>>>>>>> is added, it comes from loongson ipi mostly. And it defined four
>>>>>>> abstract
>>>>>>> interfaces which can be used for MIPS 3A4000 and Loongarch 3A5000
>>>>>>> machine,
>>>>>>> also can be used for 3A5000 irqchip in kernel mode soon.
>>>>>>>
>>>>>>> Also Loongarch ipi and loongson ipi device are added here, it inherits
>>>>>>> from base class TYPE_LOONGSON_IPI_COMMON. Loongarch ipi is tested,
>>>>>>> loongson ipi device only passes to compile and make check, it is not
>>>>>>> tested.
>>>>>>>
>>>>>>> Bibo Mao (4):
>>>>>>> hw/intc/loongson_ipi_common: Add loongson ipi common class
>>>>>>> hw/intc/loongarch_ipi: Add loongarch ipi support
>>>>>>> hw/loongarch/virt: Replace loongson ipi with loongarch ipi
>>>>>>> hw/intc/loongson_ipi: reconstruct driver inherit from common class
>>>>>>
>>>>>> I'll try to respin a clearer v3.
>>>>> I am ok with it since it solve the problem, and it is suitable for
>>>>> 9.1 release. Only that in the long time we hope that intc emulation
>>>>> driver has common base class + tcg/kvm driver, similar with other
>>>>> architecture.
>>>>>
>>>> Sorry for the confusion, I had thought it was another topic.
>>>>
>>>> Thanks for pointing out the problem and welcome the v3 version.
>>>
>>> Please do not post v3, let me post it.
>> Hi Philippe,
>>
>> QEMU 9.1 is coming to soft frozen stage, do you have enough time working
>> on it? Is it ok to use bugfix patch for 9.1 release version?
Yeah, trying to do my best here. Again I expect splitting your work
in multiple commits would have accelerated the review process.
>
> Bug fix is always qualified between soft freeze and release.
>
> I tested the series for MIPS yesterday and can confirm it do work.
>
> Will give my tags on v3.
Thanks, I think I'm getting sick so I'll post what I did so far,
only build-tested so far, but my brain is not working well (fever?)
so I'll let Bibo/you resolve any issues with v3 (respinning if
required) and then either Song or me can queue the result next
week before the freeze.
Regards,
Phil.
>> https://lore.kernel.org/all/20240627125819.62779-2-philmd@linaro.org/
>>
>> After 9.1 is released, there will be enough time for patch v3.
>>
>> Regards
>> Bibo, Mao
>
^ permalink raw reply [flat|nested] 17+ messages in thread