From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NlLTe-0001tC-DR for qemu-devel@nongnu.org; Sat, 27 Feb 2010 07:08:58 -0500 Received: from [199.232.76.173] (port=59634 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NlLTd-0001si-Rw for qemu-devel@nongnu.org; Sat, 27 Feb 2010 07:08:57 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NlLTd-0002vg-13 for qemu-devel@nongnu.org; Sat, 27 Feb 2010 07:08:57 -0500 Received: from mail-iw0-f194.google.com ([209.85.223.194]:60804) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NlLTc-0002vc-IJ for qemu-devel@nongnu.org; Sat, 27 Feb 2010 07:08:56 -0500 Received: by iwn32 with SMTP id 32so1048648iwn.18 for ; Sat, 27 Feb 2010 04:08:55 -0800 (PST) MIME-Version: 1.0 Sender: shocklink99@gmail.com From: shocklink99@yahoo.com.tw Date: Sat, 27 Feb 2010 20:08:33 +0800 Message-ID: <408d4ad1002270408o7749a4e7u603a6e7bf6fdfc5f@mail.gmail.com> Content-Type: multipart/alternative; boundary=001485eba2e8349467048093e1b8 Subject: [Qemu-devel] How to precisely monitor all the memory references in QEMU to feed the cache model List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --001485eba2e8349467048093e1b8 Content-Type: text/plain; charset=ISO-8859-1 Hi, I'm adding a cache model into QEMU 0.12 I have encountered a problem that the cache miss error rate was high compared to real platform Creator(arm926) . I used the QEMU integrator board to run the experiment. I've modified softmmu_header.h softmmu_template.h target-arm/translate.c e.g. in softmmu_header.h glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) I monitored the ptr, I know that ptr is the access address e.g. in softmmu_template.h glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr e.g. target-arm/translate.c static inline TCGv gen_ld8s(TCGv addr, int index) { TCGv tmp = new_tmp(); gen_helper_cache_access(addr , tcg_const_i32(1) ); tcg_gen_qemu_ld8s(tmp, addr, index); return tmp; } I had taken care of all the related function. Is there anything I ignored when running with the model? I have also reduce the timer interrupt to make it closed enough with the real platform. SO the context switch overhead should be little enough. --001485eba2e8349467048093e1b8 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi,
I'm adding a cache model=A0 into QEMU= 0.12
I have encountered a problem that the cache miss error rate was hi= gh compared to real platform Creator(arm926) .
I used the QEMU integrato= r board to run the experiment.
I've modified
softmmu_header.h
softmmu_template.h
target-arm= /translate.c

e.g. in softmmu_header.h
glue(glue(ld, USUFFIX), ME= MSUFFIX)(target_ulong ptr)
I monitored the ptr, I know that ptr is the a= ccess address

e.g. in softmmu_template.h
glue(glue(__ld, SUFFIX), MMUSUFFIX)(targe= t_ulong addr


e.g. target-arm/translate.c
static inline TCGv g= en_ld8s(TCGv addr, int index)
{
=A0=A0=A0 TCGv tmp =3D new_tmp();
=
=A0=A0=A0 gen_helper_cache_access(addr , tcg_const_i32(1) );

=A0=A0= =A0 tcg_gen_qemu_ld8s(tmp, addr, index);
=A0=A0=A0 return tmp;
}
=
I had taken care of all the related function.
Is there=A0 anything I= ignored when running with the model?

I have also reduce the timer interrupt to make it closed enough with th= e real platform.
SO the context switch overhead should be little enough= .

--001485eba2e8349467048093e1b8--