From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by monty-python.gnu.org with tmda-scanned (Exim 4.34) id 1BT85i-000301-UI for qemu-devel@nongnu.org; Wed, 26 May 2004 19:45:47 -0400 Received: from mail by monty-python.gnu.org with spam-scanned (Exim 4.34) id 1BT858-0002w6-PT for qemu-devel@nongnu.org; Wed, 26 May 2004 19:45:43 -0400 Received: from [193.252.22.29] (helo=mwinf0203.wanadoo.fr) by monty-python.gnu.org with esmtp (Exim 4.34) id 1BT7CJ-0002eT-2Y for qemu-devel@nongnu.org; Wed, 26 May 2004 18:48:31 -0400 Received: from bellard.org (ATuileries-112-1-3-7.w81-48.abo.wanadoo.fr [81.48.134.7]) by mwinf0203.wanadoo.fr (SMTP Server) with ESMTP id 48A0D1000171 for ; Thu, 27 May 2004 00:48:30 +0200 (CEST) Message-ID: <40B51F4D.8000307@bellard.org> Date: Thu, 27 May 2004 00:50:53 +0200 From: Fabrice Bellard MIME-Version: 1.0 Subject: Re: [Qemu-devel] PCI: Memory mapped / ROM resources References: <1085582014.20025.11.camel@sherbert> <40B4FC37.7080601@bellard.org> <1085603535.4321.8.camel@sherbert> In-Reply-To: <1085603535.4321.8.camel@sherbert> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Gianni Tedesco wrote: > I'm adding a host PCI proxy layer that works under Linux, ie: make host > PCI devices appear within the emulator. Similar to 'pcidev' on bochs, > but without a custom kernel module, and some minor performance > enhancements. I ought to have a patch ready by tomorrow evening. Interesting. How do you redirect irqs ? > PS. I am using mmap() on /proc/pci/bus/XX/YY.Z nodes to map PCI > registers, probably there is a nice way to allow the code generator to > generate accesses directly on to these vmas? It's probably not that much > of a win in any case, but interesting. You'd better defines memory access callbacks. It could be possible to define RAM memory areas for which the access is optimised internally by the CPU core, but currently they must stay in the phys_ram_base array. Fabrice.