From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com
Subject: Re: [PATCH v2 05/10] target/riscv: Convert env->virt to a bool env->virt_enabled
Date: Mon, 27 Mar 2023 11:09:09 -0700 [thread overview]
Message-ID: <40cca628-0c8b-7cdf-d779-16ece30a89ba@linaro.org> (raw)
In-Reply-To: <20230327080858.39703-6-liweiwei@iscas.ac.cn>
On 3/27/23 01:08, Weiwei Li wrote:
> From: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
>
> Currently we only use the env->virt to encode the virtual mode enabled
> status. Let's make it a bool type.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Message-ID:<20230325145348.1208-1-zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu_bits.h | 3 ---
> target/riscv/cpu_helper.c | 6 +++---
> target/riscv/machine.c | 6 +++---
> target/riscv/translate.c | 4 ++--
> 5 files changed, 9 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2023-03-27 18:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 8:08 [PATCH v2 00/10] target/riscv: Simplification for RVH related check and code style fix Weiwei Li
2023-03-27 8:08 ` [PATCH v2 01/10] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Weiwei Li
2023-04-05 5:17 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 02/10] target/riscv: Remove redundant check on RVH Weiwei Li
2023-04-05 5:17 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 03/10] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Weiwei Li
2023-04-05 5:18 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 04/10] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Weiwei Li
2023-04-05 5:20 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 05/10] target/riscv: Convert env->virt to a bool env->virt_enabled Weiwei Li
2023-03-27 18:09 ` Richard Henderson [this message]
2023-04-05 5:26 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 06/10] target/riscv: Remove riscv_cpu_virt_enabled() Weiwei Li
2023-03-27 18:10 ` Richard Henderson
2023-03-28 1:14 ` LIU Zhiwei
2023-04-05 5:26 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 07/10] target/riscv: Remove redundant parentheses Weiwei Li
2023-04-05 5:27 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 08/10] target/riscv: Fix format for indentation Weiwei Li
2023-04-05 5:29 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 09/10] target/riscv: Fix format for comments Weiwei Li
2023-04-05 5:28 ` Alistair Francis
2023-03-27 8:08 ` [PATCH v2 10/10] target/riscv: Fix lines with over 80 characters Weiwei Li
2023-04-05 5:30 ` Alistair Francis
2023-04-05 5:30 ` [PATCH v2 00/10] target/riscv: Simplification for RVH related check and code style fix Alistair Francis
2023-04-05 5:39 ` Alistair Francis
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