[PATCH v2 00/11] Fix bugs for LoongArch virt machine

[PATCH v2 00/11] Fix bugs for LoongArch virt machine

[Xiaojuan Yang]

This series fix some bugs for LoongArch virt machine. Including
RTC device emulation, ECFG reg emulation, timer clear function,
and IPI device function, etc.

Xiaojuan Yang (11):
  hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function
  hw/rtc/ls7a_rtc: Fix timer call back function
  hw/rtc/ls7a_rtc: Remove unimplemented device in realized function
  hw/rtc/ls7a_rtc: Add reset function
  hw/rtc/ls7a_rtc: Fix rtc enable and disable function
  hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in
    toy_time_to_val()
  hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors
  target/loongarch: Fix the meaning of ECFG reg's VS field
  target/loongarch: Add lock when writing timer clear reg
  hw/intc/loongarch_ipi: Fix ipi device access of 64bits
  hw/intc/loongarch_ipi: Fix mail send and any send function

 hw/intc/loongarch_ipi.c         |  83 +++++++++++++-------
 hw/loongarch/loongson3.c        |   5 +-
 hw/rtc/ls7a_rtc.c               | 131 +++++++++++++-------------------
 include/hw/intc/loongarch_ipi.h |   7 +-
 target/loongarch/cpu.c          |   4 +
 target/loongarch/csr_helper.c   |   2 +
 6 files changed, 122 insertions(+), 110 deletions(-)

-- 
2.31.1

[PATCH 01/11] hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function

[Xiaojuan Yang]

1. Initialize the tm struct in toymatch_write() and ls7a_toy_start() to
   fix uninitialized bugs.
2. Fix toymatch_val_to_time function. By the document, when we calculate
   the expiration year, we should first get current year, and replace the
   0-5 bits with toymatch's 26-31 bits.

Fixes: Coverity CID 1489766, 1489763

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index fe6710310f..b88a90de8b 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -148,8 +148,9 @@ static inline uint64_t toy_time_to_val_year(struct tm tm)
     return year;
 }
 
-static inline void toymatch_val_to_time(uint64_t val, struct tm *tm)
+static inline void toymatch_val_to_time(LS7ARtcState *s, uint64_t val, struct tm *tm)
 {
+    qemu_get_timedate(tm, s->offset_toy);
     tm->tm_sec = FIELD_EX32(val, TOY_MATCH, SEC);
     tm->tm_min = FIELD_EX32(val, TOY_MATCH, MIN);
     tm->tm_hour = FIELD_EX32(val, TOY_MATCH, HOUR);
@@ -158,17 +159,18 @@ static inline void toymatch_val_to_time(uint64_t val, struct tm *tm)
     tm->tm_year += (FIELD_EX32(val, TOY_MATCH, YEAR) - (tm->tm_year & 0x3f));
 }
 
-static void toymatch_write(LS7ARtcState *s, struct tm *tm, uint64_t val, int num)
+static void toymatch_write(LS7ARtcState *s, uint64_t val, int num)
 {
     int64_t now, expire_time;
+    struct tm tm = {};
 
     /* it do not support write when toy disabled */
     if (toy_enabled(s)) {
         s->toymatch[num] = val;
         /* caculate expire time */
         now = qemu_clock_get_ms(rtc_clock);
-        toymatch_val_to_time(val, tm);
-        expire_time = now + (qemu_timedate_diff(tm) - s->offset_toy) * 1000;
+        toymatch_val_to_time(s, val, &tm);
+        expire_time = now + (qemu_timedate_diff(&tm) - s->offset_toy) * 1000;
         timer_mod(s->toy_timer[num], expire_time);
     }
 }
@@ -223,7 +225,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 {
     int i;
     uint64_t expire_time, now;
-    struct tm tm;
+    struct tm tm = {};
     /*
      * need to recaculate toy offset
      * and expire time when enable it.
@@ -236,7 +238,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 
     /* recaculate expire time and enable timer */
     for (i = 0; i < TIMER_NUMS; i++) {
-        toymatch_val_to_time(s->toymatch[i], &tm);
+        toymatch_val_to_time(s, s->toymatch[i], &tm);
         expire_time = now + (qemu_timedate_diff(&tm) - s->offset_toy) * 1000;
         timer_mod(s->toy_timer[i], expire_time);
     }
@@ -352,13 +354,13 @@ static void ls7a_rtc_write(void *opaque, hwaddr addr,
         }
         break;
     case SYS_TOYMATCH0:
-        toymatch_write(s, &tm, val, 0);
+        toymatch_write(s, val, 0);
         break;
     case SYS_TOYMATCH1:
-        toymatch_write(s, &tm, val, 1);
+        toymatch_write(s, val, 1);
         break;
     case SYS_TOYMATCH2:
-        toymatch_write(s, &tm, val, 2);
+        toymatch_write(s, val, 2);
         break;
     case SYS_RTCCTRL:
         /* get old ctrl */
-- 
2.31.1

Re: [PATCH 01/11] hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function

[Richard Henderson]

On 7/1/22 15:03, Xiaojuan Yang wrote:
> 1. Initialize the tm struct in toymatch_write() and ls7a_toy_start() to
>     fix uninitialized bugs.
> 2. Fix toymatch_val_to_time function. By the document, when we calculate
>     the expiration year, we should first get current year, and replace the
>     0-5 bits with toymatch's 26-31 bits.
> 
> Fixes: Coverity CID 1489766, 1489763
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 02/11] hw/rtc/ls7a_rtc: Fix timer call back function

[Xiaojuan Yang]

Replace qemu_irq_pulse with qemu_irq_raise in ls7a_timer_cb function
to keep consistent with hardware behavior when raise irq.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index b88a90de8b..780144b9da 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -425,7 +425,7 @@ static void toy_timer_cb(void *opaque)
     LS7ARtcState *s = opaque;
 
     if (toy_enabled(s)) {
-        qemu_irq_pulse(s->irq);
+        qemu_irq_raise(s->irq);
     }
 }
 
@@ -434,7 +434,7 @@ static void rtc_timer_cb(void *opaque)
     LS7ARtcState *s = opaque;
 
     if (rtc_enabled(s)) {
-        qemu_irq_pulse(s->irq);
+        qemu_irq_raise(s->irq);
     }
 }
 
-- 
2.31.1

Re: [PATCH 02/11] hw/rtc/ls7a_rtc: Fix timer call back function

[Richard Henderson]

On 7/1/22 15:03, Xiaojuan Yang wrote:
> Replace qemu_irq_pulse with qemu_irq_raise in ls7a_timer_cb function
> to keep consistent with hardware behavior when raise irq.
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH 03/11] hw/rtc/ls7a_rtc: Remove unimplemented device in realized function

[Xiaojuan Yang]

Remove the unimplemented device when realized ls7a RTC, as it is not uesd.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index 780144b9da..f1e7a660e9 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -461,7 +461,6 @@ static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
     d->save_toy_year = 0;
     d->save_rtc = 0;
 
-    create_unimplemented_device("mmio fallback 1", 0x10013ffc, 0x4);
 }
 
 static int ls7a_rtc_pre_save(void *opaque)
-- 
2.31.1

Re: [PATCH 03/11] hw/rtc/ls7a_rtc: Remove unimplemented device in realized function

[Richard Henderson]

On 7/1/22 15:03, Xiaojuan Yang wrote:
> Remove the unimplemented device when realized ls7a RTC, as it is not uesd.
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
>   hw/rtc/ls7a_rtc.c | 1 -
>   1 file changed, 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 04/11] hw/rtc/ls7a_rtc: Add reset function

[Xiaojuan Yang]

Add ls7a rtc reset function to delete timers and clear regs when rtc reset.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index f1e7a660e9..eb10cdb451 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -463,6 +463,25 @@ static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
 
 }
 
+/* delete timer and clear reg when reset */
+static void ls7a_rtc_reset(DeviceState *dev)
+{
+    int i;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    LS7ARtcState *d = LS7A_RTC(sbd);
+    for (i = 0; i < TIMER_NUMS; i++) {
+        if (toy_enabled(d)) {
+            timer_del(d->toy_timer[i]);
+        }
+        if (rtc_enabled(d)) {
+            timer_del(d->rtc_timer[i]);
+        }
+        d->toymatch[i] = 0;
+        d->rtcmatch[i] = 0;
+    }
+    d->cntrctl = 0;
+}
+
 static int ls7a_rtc_pre_save(void *opaque)
 {
     LS7ARtcState *s = LS7A_RTC(opaque);
@@ -511,6 +530,7 @@ static void ls7a_rtc_class_init(ObjectClass *klass, void *data)
     DeviceClass *dc = DEVICE_CLASS(klass);
     dc->vmsd = &vmstate_ls7a_rtc;
     dc->realize = ls7a_rtc_realize;
+    dc->reset = ls7a_rtc_reset;
     dc->desc = "ls7a rtc";
 }
 
-- 
2.31.1

[PATCH 05/11] hw/rtc/ls7a_rtc: Fix rtc enable and disable function

[Xiaojuan Yang]

Fix ls7a rtc enable and disable function. When rtc disabled, it do
not support to read or write, but the real time is still continue,
so we need not neither save the time nor update the rtc offset.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 60 ++++++-----------------------------------------
 1 file changed, 7 insertions(+), 53 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index eb10cdb451..a36aeea9dd 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -72,9 +72,6 @@ struct LS7ARtcState {
      */
     int64_t offset_toy;
     int64_t offset_rtc;
-    uint64_t save_toy_mon;
-    uint64_t save_toy_year;
-    uint64_t save_rtc;
     int64_t data;
     int tidx;
     uint32_t toymatch[3];
@@ -140,14 +137,6 @@ static inline uint64_t toy_time_to_val_mon(struct tm tm)
     return val;
 }
 
-static inline uint64_t toy_time_to_val_year(struct tm tm)
-{
-    uint64_t year;
-
-    year = tm.tm_year;
-    return year;
-}
-
 static inline void toymatch_val_to_time(LS7ARtcState *s, uint64_t val, struct tm *tm)
 {
     qemu_get_timedate(tm, s->offset_toy);
@@ -191,14 +180,6 @@ static void rtcmatch_write(LS7ARtcState *s, uint64_t val, int num)
 static void ls7a_toy_stop(LS7ARtcState *s)
 {
     int i;
-    struct tm tm;
-    /*
-     * save time when disabled toy,
-     * because toy time not add counters.
-     */
-    qemu_get_timedate(&tm, s->offset_toy);
-    s->save_toy_mon = toy_time_to_val_mon(tm);
-    s->save_toy_year = toy_time_to_val_year(tm);
 
     /* delete timers, and when re-enabled, recaculate expire time */
     for (i = 0; i < TIMER_NUMS; i++) {
@@ -209,11 +190,6 @@ static void ls7a_toy_stop(LS7ARtcState *s)
 static void ls7a_rtc_stop(LS7ARtcState *s)
 {
     int i;
-    uint64_t time;
-
-    /* save rtc time */
-    time = ls7a_rtc_ticks() + s->offset_rtc;
-    s->save_rtc = time;
 
     /* delete timers, and when re-enabled, recaculate expire time */
     for (i = 0; i < TIMER_NUMS; i++) {
@@ -226,14 +202,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
     int i;
     uint64_t expire_time, now;
     struct tm tm = {};
-    /*
-     * need to recaculate toy offset
-     * and expire time when enable it.
-     */
-    toy_val_to_time_mon(s->save_toy_mon, &tm);
-    toy_val_to_time_year(s->save_toy_year, &tm);
 
-    s->offset_toy = qemu_timedate_diff(&tm);
     now = qemu_clock_get_ms(rtc_clock);
 
     /* recaculate expire time and enable timer */
@@ -247,14 +216,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 static void ls7a_rtc_start(LS7ARtcState *s)
 {
     int i;
-    uint64_t expire_time, now;
-
-    /*
-     * need to recaculate rtc offset
-     * and expire time when enable it.
-     */
-    now = ls7a_rtc_ticks();
-    s->offset_rtc = s->save_rtc - now;
+    uint64_t expire_time;
 
     /* recaculate expire time and enable timer */
     for (i = 0; i < TIMER_NUMS; i++) {
@@ -271,23 +233,21 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, unsigned size)
 
     switch (addr) {
     case SYS_TOYREAD0:
-        /* if toy disabled, read save toy time */
         if (toy_enabled(s)) {
             qemu_get_timedate(&tm, s->offset_toy);
             val = toy_time_to_val_mon(tm);
         } else {
-            /* read save mon val */
-            val = s->save_toy_mon;
+            /* return 0 when toy disabled */
+            val = 0;
         }
         break;
     case SYS_TOYREAD1:
-        /* if toy disabled, read save toy time */
         if (toy_enabled(s)) {
             qemu_get_timedate(&tm, s->offset_toy);
             val = tm.tm_year;
         } else {
-            /* read save year val */
-            val = s->save_toy_year;
+            /* return 0 when toy disabled */
+            val = 0;
         }
         break;
     case SYS_TOYMATCH0:
@@ -303,11 +263,11 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, unsigned size)
         val = s->cntrctl;
         break;
     case SYS_RTCREAD0:
-        /* if rtc disabled, read save rtc time */
         if (rtc_enabled(s)) {
             val = ls7a_rtc_ticks() + s->offset_rtc;
         } else {
-            val = s->save_rtc;
+            /* return 0 when rtc disabled */
+            val = 0;
         }
         break;
     case SYS_RTCMATCH0:
@@ -457,9 +417,6 @@ static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
     }
     d->offset_toy = 0;
     d->offset_rtc = 0;
-    d->save_toy_mon = 0;
-    d->save_toy_year = 0;
-    d->save_rtc = 0;
 
 }
 
@@ -515,9 +472,6 @@ static const VMStateDescription vmstate_ls7a_rtc = {
     .fields = (VMStateField[]) {
         VMSTATE_INT64(offset_toy, LS7ARtcState),
         VMSTATE_INT64(offset_rtc, LS7ARtcState),
-        VMSTATE_UINT64(save_toy_mon, LS7ARtcState),
-        VMSTATE_UINT64(save_toy_year, LS7ARtcState),
-        VMSTATE_UINT64(save_rtc, LS7ARtcState),
         VMSTATE_UINT32_ARRAY(toymatch, LS7ARtcState, TIMER_NUMS),
         VMSTATE_UINT32_ARRAY(rtcmatch, LS7ARtcState, TIMER_NUMS),
         VMSTATE_UINT32(cntrctl, LS7ARtcState),
-- 
2.31.1

Re: [PATCH 05/11] hw/rtc/ls7a_rtc: Fix rtc enable and disable function

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> Fix ls7a rtc enable and disable function. When rtc disabled, it do
> not support to read or write, but the real time is still continue,
> so we need not neither save the time nor update the rtc offset.
> 
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> ---
>   hw/rtc/ls7a_rtc.c | 60 ++++++-----------------------------------------
>   1 file changed, 7 insertions(+), 53 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 06/11] hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val()

[Xiaojuan Yang]

Use pointer as arguments in toy_time_to_val() instead of struct tm.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index a36aeea9dd..85cd2d22a5 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -125,15 +125,15 @@ static inline void toy_val_to_time_year(uint64_t toy_year, struct tm *tm)
 }
 
 /* parse struct tm to toy value */
-static inline uint64_t toy_time_to_val_mon(struct tm tm)
+static inline uint64_t toy_time_to_val_mon(struct tm *tm)
 {
     uint64_t val = 0;
 
-    val = FIELD_DP32(val, TOY, MON, tm.tm_mon + 1);
-    val = FIELD_DP32(val, TOY, DAY, tm.tm_mday);
-    val = FIELD_DP32(val, TOY, HOUR, tm.tm_hour);
-    val = FIELD_DP32(val, TOY, MIN, tm.tm_min);
-    val = FIELD_DP32(val, TOY, SEC, tm.tm_sec);
+    val = FIELD_DP32(val, TOY, MON, tm->tm_mon + 1);
+    val = FIELD_DP32(val, TOY, DAY, tm->tm_mday);
+    val = FIELD_DP32(val, TOY, HOUR, tm->tm_hour);
+    val = FIELD_DP32(val, TOY, MIN, tm->tm_min);
+    val = FIELD_DP32(val, TOY, SEC, tm->tm_sec);
     return val;
 }
 
@@ -235,7 +235,7 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, unsigned size)
     case SYS_TOYREAD0:
         if (toy_enabled(s)) {
             qemu_get_timedate(&tm, s->offset_toy);
-            val = toy_time_to_val_mon(tm);
+            val = toy_time_to_val_mon(&tm);
         } else {
             /* return 0 when toy disabled */
             val = 0;
-- 
2.31.1

Re: [PATCH 06/11] hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val()

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> Use pointer as arguments in toy_time_to_val() instead of struct tm.
> 
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> ---
>   hw/rtc/ls7a_rtc.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 07/11] hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors

[Xiaojuan Yang]

Fix 'calculate' spelling errors.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/rtc/ls7a_rtc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index 85cd2d22a5..e8b75701e4 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -156,7 +156,7 @@ static void toymatch_write(LS7ARtcState *s, uint64_t val, int num)
     /* it do not support write when toy disabled */
     if (toy_enabled(s)) {
         s->toymatch[num] = val;
-        /* caculate expire time */
+        /* calculate expire time */
         now = qemu_clock_get_ms(rtc_clock);
         toymatch_val_to_time(s, val, &tm);
         expire_time = now + (qemu_timedate_diff(&tm) - s->offset_toy) * 1000;
@@ -171,7 +171,7 @@ static void rtcmatch_write(LS7ARtcState *s, uint64_t val, int num)
     /* it do not support write when toy disabled */
     if (rtc_enabled(s)) {
         s->rtcmatch[num] = val;
-        /* caculate expire time */
+        /* calculate expire time */
         expire_ns = ticks_to_ns(val) - ticks_to_ns(s->offset_rtc);
         timer_mod_ns(s->rtc_timer[num], expire_ns);
     }
@@ -181,7 +181,7 @@ static void ls7a_toy_stop(LS7ARtcState *s)
 {
     int i;
 
-    /* delete timers, and when re-enabled, recaculate expire time */
+    /* delete timers, and when re-enabled, recalculate expire time */
     for (i = 0; i < TIMER_NUMS; i++) {
         timer_del(s->toy_timer[i]);
     }
@@ -191,7 +191,7 @@ static void ls7a_rtc_stop(LS7ARtcState *s)
 {
     int i;
 
-    /* delete timers, and when re-enabled, recaculate expire time */
+    /* delete timers, and when re-enabled, recalculate expire time */
     for (i = 0; i < TIMER_NUMS; i++) {
         timer_del(s->rtc_timer[i]);
     }
@@ -205,7 +205,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 
     now = qemu_clock_get_ms(rtc_clock);
 
-    /* recaculate expire time and enable timer */
+    /* recalculate expire time and enable timer */
     for (i = 0; i < TIMER_NUMS; i++) {
         toymatch_val_to_time(s, s->toymatch[i], &tm);
         expire_time = now + (qemu_timedate_diff(&tm) - s->offset_toy) * 1000;
@@ -218,7 +218,7 @@ static void ls7a_rtc_start(LS7ARtcState *s)
     int i;
     uint64_t expire_time;
 
-    /* recaculate expire time and enable timer */
+    /* recalculate expire time and enable timer */
     for (i = 0; i < TIMER_NUMS; i++) {
         expire_time = ticks_to_ns(s->rtcmatch[i]) - ticks_to_ns(s->offset_rtc);
         timer_mod_ns(s->rtc_timer[i], expire_time);
-- 
2.31.1

Re: [PATCH 07/11] hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> Fix 'calculate' spelling errors.
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 08/11] target/loongarch: Fix the meaning of ECFG reg's VS field

[Xiaojuan Yang]

By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 target/loongarch/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4c8f96bc3a..04e5e47da4 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
 
+    if (vec_size) {
+        vec_size = (1 << vec_size) * 4;
+    }
+
     if  (cs->exception_index == EXCCODE_INT) {
         /* Interrupt */
         uint32_t vector = 0;
-- 
2.31.1

Re: [PATCH 08/11] target/loongarch: Fix the meaning of ECFG reg's VS field

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> By the manual of LoongArch CSR, the VS field(18:16 bits) of
> ECFG reg means that the number of instructions between each
> exception entry is 2^VS.

Is it a typo in the manual that says "2VS", i.e. multiplication?

If so,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
>   target/loongarch/cpu.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 4c8f96bc3a..04e5e47da4 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
>       env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
>       env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
>   
> +    if (vec_size) {
> +        vec_size = (1 << vec_size) * 4;
> +    }
> +
>       if  (cs->exception_index == EXCCODE_INT) {
>           /* Interrupt */
>           uint32_t vector = 0;

Re: [PATCH 08/11] target/loongarch: Fix the meaning of ECFG reg's VS field

[gaosong]

On 2022/7/4 下午1:18, Richard Henderson wrote:
> On 7/1/22 15:04, Xiaojuan Yang wrote:
>> By the manual of LoongArch CSR, the VS field(18:16 bits) of
>> ECFG reg means that the number of instructions between each
>> exception entry is 2^VS.
>
> Is it a typo in the manual that says "2VS", i.e. multiplication?
>
Is '2^VS',  the manual is wrong.

Thanks.
Song Gao
> If so,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
>>
>> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> ---
>>   target/loongarch/cpu.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index 4c8f96bc3a..04e5e47da4 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState 
>> *cs)
>>       env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
>>       env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
>>   +    if (vec_size) {
>> +        vec_size = (1 << vec_size) * 4;
>> +    }
>> +
>>       if  (cs->exception_index == EXCCODE_INT) {
>>           /* Interrupt */
>>           uint32_t vector = 0;
>

[PATCH 09/11] target/loongarch: Add lock when writing timer clear reg

[Xiaojuan Yang]

There is such error info when running linux kernel:
    tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()).
    calling stack:
    #0 in raise () at /lib64/libc.so.6
    #1 in abort () at /lib64/libc.so.6
    #2 in g_assertion_message_expr.cold () at /lib64/libglib-2.0.so.0
    #3 in g_assertion_message_expr () at /lib64/libglib-2.0.so.0
    #4 in tcg_handle_interrupt (cpu=0x632000030800, mask=2) at ../accel/tcg/tcg-accel-ops.c:79
    #5 in cpu_interrupt (cpu=0x632000030800, mask=2) at ../softmmu/cpus.c:248
    #6 in loongarch_cpu_set_irq (opaque=0x632000030800, irq=11, level=0)
       at ../target/loongarch/cpu.c:100
    #7 in helper_csrwr_ticlr (env=0x632000039440, val=1) at ../target/loongarch/csr_helper.c:85
    #8 in code_gen_buffer ()
    #9 in cpu_tb_exec (cpu=0x632000030800, itb=0x7fff946ac280, tb_exit=0x7ffe4fcb6c30)
       at ../accel/tcg/cpu-exec.c:358

Add mutex iothread lock around loongarch_cpu_set_irq in csrwr_ticlr() to
fix the bug.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 target/loongarch/csr_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c
index 24a9389364..7e02787895 100644
--- a/target/loongarch/csr_helper.c
+++ b/target/loongarch/csr_helper.c
@@ -81,7 +81,9 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
     int64_t old_v = 0;
 
     if (val & 0x1) {
+        qemu_mutex_lock_iothread();
         loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0);
+        qemu_mutex_unlock_iothread();
     }
     return old_v;
 }
-- 
2.31.1

Re: [PATCH 09/11] target/loongarch: Add lock when writing timer clear reg

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> There is such error info when running linux kernel:
>      tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()).
>      calling stack:
>      #0 in raise () at /lib64/libc.so.6
>      #1 in abort () at /lib64/libc.so.6
>      #2 in g_assertion_message_expr.cold () at /lib64/libglib-2.0.so.0
>      #3 in g_assertion_message_expr () at /lib64/libglib-2.0.so.0
>      #4 in tcg_handle_interrupt (cpu=0x632000030800, mask=2) at ../accel/tcg/tcg-accel-ops.c:79
>      #5 in cpu_interrupt (cpu=0x632000030800, mask=2) at ../softmmu/cpus.c:248
>      #6 in loongarch_cpu_set_irq (opaque=0x632000030800, irq=11, level=0)
>         at ../target/loongarch/cpu.c:100
>      #7 in helper_csrwr_ticlr (env=0x632000039440, val=1) at ../target/loongarch/csr_helper.c:85
>      #8 in code_gen_buffer ()
>      #9 in cpu_tb_exec (cpu=0x632000030800, itb=0x7fff946ac280, tb_exit=0x7ffe4fcb6c30)
>         at ../accel/tcg/cpu-exec.c:358
> 
> Add mutex iothread lock around loongarch_cpu_set_irq in csrwr_ticlr() to
> fix the bug.
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH 10/11] hw/intc/loongarch_ipi: Fix ipi device access of 64bits

[Xiaojuan Yang]

In general loongarch ipi device, 32bit registers is emulated, however for
anysend/mailsend device only 64bit register access is supported. So separate
the ipi memory region into two regions, including 32 bits and 64 bits.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/intc/loongarch_ipi.c         | 38 +++++++++++++++++++++++++++------
 hw/loongarch/loongson3.c        |  5 ++++-
 include/hw/intc/loongarch_ipi.h |  7 +++---
 3 files changed, 39 insertions(+), 11 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 66bee93675..553e88703d 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -150,12 +150,6 @@ static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
     case IOCSR_IPI_SEND:
         ipi_send(val);
         break;
-    case IOCSR_MAIL_SEND:
-        mail_send(val);
-        break;
-    case IOCSR_ANY_SEND:
-        any_send(val);
-        break;
     default:
         qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
         break;
@@ -172,6 +166,32 @@ static const MemoryRegionOps loongarch_ipi_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
+/* mail send and any send only support writeq */
+static void loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
+                                 unsigned size)
+{
+    addr &= 0xfff;
+    switch (addr) {
+    case MAIL_SEND_OFFSET:
+        mail_send(val);
+        break;
+    case ANY_SEND_OFFSET:
+        any_send(val);
+        break;
+    default:
+       break;
+    }
+}
+
+static const MemoryRegionOps loongarch_ipi64_ops = {
+    .write = loongarch_ipi_writeq,
+    .impl.min_access_size = 8,
+    .impl.max_access_size = 8,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 8,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
 static void loongarch_ipi_init(Object *obj)
 {
     int cpu;
@@ -187,8 +207,12 @@ static void loongarch_ipi_init(Object *obj)
     lams = LOONGARCH_MACHINE(machine);
     for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
         memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
-                            &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x100);
+                            &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
         sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
+
+        memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
+                              &lams->ipi_core[cpu], "loongarch_ipi64_iocsr", 0x118);
+        sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]);
         qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1);
     }
 }
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index bd20ebbb78..0cc023bd3c 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -230,7 +230,10 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
         /* IPI iocsr memory region */
         memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
-                                    cpu));
+                                    cpu * 2));
+        memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
+                                    sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+                                    cpu * 2 + 1));
         /* extioi iocsr memory region */
         memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index 996ed7ea93..0ee48fca55 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -24,8 +24,9 @@
 #define IOCSR_MAIL_SEND       0x48
 #define IOCSR_ANY_SEND        0x158
 
-/* IPI system memory address */
-#define IPI_SYSTEM_MEM        0x1fe01000
+#define MAIL_SEND_ADDR        (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET      0
+#define ANY_SEND_OFFSET       (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
 
 #define MAX_IPI_CORE_NUM      4
 #define MAX_IPI_MBX_NUM       4
@@ -46,7 +47,7 @@ typedef struct IPICore {
 struct LoongArchIPI {
     SysBusDevice parent_obj;
     MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
-    MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM];
+    MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
 };
 
 #endif
-- 
2.31.1

Re: [PATCH 10/11] hw/intc/loongarch_ipi: Fix ipi device access of 64bits

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> +static const MemoryRegionOps loongarch_ipi64_ops = {
> +    .write = loongarch_ipi_writeq,
> +    .impl.min_access_size = 8,
> +    .impl.max_access_size = 8,
> +    .valid.min_access_size = 4,
> +    .valid.max_access_size = 8,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +};

Is it really valid to write 4 bytes instead of 8?


r~

Re: [PATCH 10/11] hw/intc/loongarch_ipi: Fix ipi device access of 64bits

[gaosong]

[-- Attachment #1: Type: text/plain, Size: 546 bytes --]


On 2022/7/4 下午1:28, Richard Henderson wrote:
> On 7/1/22 15:04, Xiaojuan Yang wrote:
>> +static const MemoryRegionOps loongarch_ipi64_ops = {
>> +    .write = loongarch_ipi_writeq,
>> +    .impl.min_access_size = 8,
>> +    .impl.max_access_size = 8,
>> +    .valid.min_access_size = 4,
>> +    .valid.max_access_size = 8,
>> +    .endianness = DEVICE_LITTLE_ENDIAN,
>> +};
>
> Is it really valid to write 4 bytes instead of 8?
>
This ipi64_ops only support 8 bytes writing,   We will correct it.

Thanks.
Song Gao

> r~

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[PATCH 11/11] hw/intc/loongarch_ipi: Fix mail send and any send function

[Xiaojuan Yang]

By the document of ipi mailsend device, byte is written only when the mask bit
is 0. The original code discards mask bit and overwrite the data always, this
patch fixes the issue.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 45 ++++++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 553e88703d..e4b1fb5366 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -50,35 +50,40 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
     return ret;
 }
 
-static int get_ipi_data(target_ulong val)
+static void send_ipi_data(CPULoongArchState *env, target_ulong val, target_ulong addr)
 {
     int i, mask, data;
 
-    data = val >> 32;
-    mask = (val >> 27) & 0xf;
-
+    data = address_space_ldl(&env->address_space_iocsr, addr,
+                             MEMTXATTRS_UNSPECIFIED, NULL);
+    mask  = 0;
     for (i = 0; i < 4; i++) {
-        if ((mask >> i) & 1) {
-            data &= ~(0xff << (i * 8));
+        /* bit 27 - 30 is mask for byte write */
+        if (val & (0x1UL << (27 + i))) {
+            mask |= 0xff << (i * 8);
         }
     }
-    return data;
+
+    data &= mask;
+    data |= (val >> 32) & ~mask;
+    address_space_stl(&env->address_space_iocsr, addr,
+                      data, MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static void ipi_send(uint64_t val)
 {
     int cpuid, data;
     CPULoongArchState *env;
+    CPUState *cs;
+    LoongArchCPU *cpu;
 
     cpuid = (val >> 16) & 0x3ff;
     /* IPI status vector */
     data = 1 << (val & 0x1f);
-    qemu_mutex_lock_iothread();
-    CPUState *cs = qemu_get_cpu(cpuid);
-    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    cs = qemu_get_cpu(cpuid);
+    cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
     loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);
-    qemu_mutex_unlock_iothread();
     address_space_stl(&env->address_space_iocsr, 0x1008,
                       data, MEMTXATTRS_UNSPECIFIED, NULL);
 
@@ -86,23 +91,23 @@ static void ipi_send(uint64_t val)
 
 static void mail_send(uint64_t val)
 {
-    int cpuid, data;
+    int cpuid;
     hwaddr addr;
     CPULoongArchState *env;
+    CPUState *cs;
+    LoongArchCPU *cpu;
 
     cpuid = (val >> 16) & 0x3ff;
     addr = 0x1020 + (val & 0x1c);
-    CPUState *cs = qemu_get_cpu(cpuid);
-    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    cs = qemu_get_cpu(cpuid);
+    cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
-    data = get_ipi_data(val);
-    address_space_stl(&env->address_space_iocsr, addr,
-                      data, MEMTXATTRS_UNSPECIFIED, NULL);
+    send_ipi_data(env, val, addr);
 }
 
 static void any_send(uint64_t val)
 {
-    int cpuid, data;
+    int cpuid;
     hwaddr addr;
     CPULoongArchState *env;
 
@@ -111,9 +116,7 @@ static void any_send(uint64_t val)
     CPUState *cs = qemu_get_cpu(cpuid);
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
-    data = get_ipi_data(val);
-    address_space_stl(&env->address_space_iocsr, addr,
-                      data, MEMTXATTRS_UNSPECIFIED, NULL);
+    send_ipi_data(env, val, addr);
 }
 
 static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
-- 
2.31.1

Re: [PATCH 11/11] hw/intc/loongarch_ipi: Fix mail send and any send function

[Richard Henderson]

On 7/1/22 15:04, Xiaojuan Yang wrote:
> By the document of ipi mailsend device, byte is written only when the mask bit
> is 0. The original code discards mask bit and overwrite the data always, this
> patch fixes the issue.
> 
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
>   hw/intc/loongarch_ipi.c | 45 ++++++++++++++++++++++-------------------
>   1 file changed, 24 insertions(+), 21 deletions(-)
> 
> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
> index 553e88703d..e4b1fb5366 100644
> --- a/hw/intc/loongarch_ipi.c
> +++ b/hw/intc/loongarch_ipi.c
> @@ -50,35 +50,40 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
>       return ret;
>   }
>   
> -static int get_ipi_data(target_ulong val)
> +static void send_ipi_data(CPULoongArchState *env, target_ulong val, target_ulong addr)
>   {
>       int i, mask, data;
>   
> -    data = val >> 32;
> -    mask = (val >> 27) & 0xf;
> -
> +    data = address_space_ldl(&env->address_space_iocsr, addr,
> +                             MEMTXATTRS_UNSPECIFIED, NULL);
> +    mask  = 0;
>       for (i = 0; i < 4; i++) {
> -        if ((mask >> i) & 1) {
> -            data &= ~(0xff << (i * 8));
> +        /* bit 27 - 30 is mask for byte write */
> +        if (val & (0x1UL << (27 + i))) {

UL suffix is never correct, since it means different things on different hosts.
Anyway, you don't any suffix here.

How often does mask == 0, so that all of val is written?  In which case you could skip the 
load.

r~

Re: [PATCH 11/11] hw/intc/loongarch_ipi: Fix mail send and any send function

[gaosong]

[-- Attachment #1: Type: text/plain, Size: 2275 bytes --]


On 2022/7/4 下午1:37, Richard Henderson wrote:
> On 7/1/22 15:04, Xiaojuan Yang wrote:
>> By the document of ipi mailsend device, byte is written only when the 
>> mask bit
>> is 0. The original code discards mask bit and overwrite the data 
>> always, this
>> patch fixes the issue.
>>
>> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> ---
>>   hw/intc/loongarch_ipi.c | 45 ++++++++++++++++++++++-------------------
>>   1 file changed, 24 insertions(+), 21 deletions(-)
>>
>> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
>> index 553e88703d..e4b1fb5366 100644
>> --- a/hw/intc/loongarch_ipi.c
>> +++ b/hw/intc/loongarch_ipi.c
>> @@ -50,35 +50,40 @@ static uint64_t loongarch_ipi_readl(void *opaque, 
>> hwaddr addr, unsigned size)
>>       return ret;
>>   }
>>   -static int get_ipi_data(target_ulong val)
>> +static void send_ipi_data(CPULoongArchState *env, target_ulong val, 
>> target_ulong addr)
>>   {
>>       int i, mask, data;
>>   -    data = val >> 32;
>> -    mask = (val >> 27) & 0xf;
>> -
>> +    data = address_space_ldl(&env->address_space_iocsr, addr,
>> +                             MEMTXATTRS_UNSPECIFIED, NULL);
>> +    mask  = 0;
>>       for (i = 0; i < 4; i++) {
>> -        if ((mask >> i) & 1) {
>> -            data &= ~(0xff << (i * 8));
>> +        /* bit 27 - 30 is mask for byte write */
>> +        if (val & (0x1UL << (27 + i))) {
>
> UL suffix is never correct, since it means different things on 
> different hosts.
> Anyway, you don't any suffix here.
>
OK, we will remove the suffix there.

> How often does mask == 0, so that all of val is written?  In which 
> case you could skip the load.
>
At most time the mask is always 0, so  we add a condition to skip the load.
like this:
+    int i, mask = 0, data = 0;
...

+   /*
+    * bit 27-30 is mask for byte writing,
+    * if the mask is 0, we should do nothing.
+    */
+   if ((val >> 27) & 0xf) {
+       data = address_space_ldl(&env->address_space_iocsr, addr,
+                                MEMTXATTRS_UNSPECIFIED, NULL);
...
}

After fix these problem, should we only send these two patches?

Thanks.
Song Gao
> r~

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Re: [PATCH 11/11] hw/intc/loongarch_ipi: Fix mail send and any send function

[Richard Henderson]

On 7/4/22 14:40, gaosong wrote:
> After fix these problem, should we only send these two patches?

Correct.  I will merge the other loongarch patches today, so you should be able to rebase 
on master.


r~

Re: [PATCH v2 00/11] Fix bugs for LoongArch virt machine

[Richard Henderson]

On 7/1/22 15:03, Xiaojuan Yang wrote:
> This series fix some bugs for LoongArch virt machine. Including
> RTC device emulation, ECFG reg emulation, timer clear function,
> and IPI device function, etc.
> 
> Xiaojuan Yang (11):
>    hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function
>    hw/rtc/ls7a_rtc: Fix timer call back function
>    hw/rtc/ls7a_rtc: Remove unimplemented device in realized function
>    hw/rtc/ls7a_rtc: Add reset function
>    hw/rtc/ls7a_rtc: Fix rtc enable and disable function
>    hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in
>      toy_time_to_val()
>    hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors
>    target/loongarch: Fix the meaning of ECFG reg's VS field
>    target/loongarch: Add lock when writing timer clear reg

I'm queueing the first 9 patches.


r~