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Thu, 08 May 2025 13:30:21 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30c39e61056sm417919a91.39.2025.05.08.13.30.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 May 2025 13:30:21 -0700 (PDT) Message-ID: <40d21813-d9b6-42f5-a439-634a8e3ccf98@linaro.org> Date: Thu, 8 May 2025 13:30:20 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/13] qemu/target-info: implement missing helpers Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, stefanha@redhat.com, peter.maydell@linaro.org, Markus Armbruster , richard.henderson@linaro.org, pbonzini@redhat.com, jsnow@redhat.com, berrange@redhat.com, thuth@redhat.com, Michael Roth References: <20250507231442.879619-1-pierrick.bouvier@linaro.org> <20250507231442.879619-9-pierrick.bouvier@linaro.org> <34d4719e-e8e9-4f2d-ad57-bb4043cb540f@linaro.org> From: Pierrick Bouvier In-Reply-To: <34d4719e-e8e9-4f2d-ad57-bb4043cb540f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/7/25 11:40 PM, Philippe Mathieu-Daudé wrote: > On 8/5/25 01:14, Pierrick Bouvier wrote: >> Add runtime helpers for target and config queries. >> >> Note: This will be reimplemented later [1] using proper information in >> TargetInfo. Meanwhile, just add a simple implementation. >> >> [1] https://patchew.org/QEMU/20250424222112.36194-1-philmd@linaro.org/20250424222112.36194-19-philmd@linaro.org/ >> >> Signed-off-by: Pierrick Bouvier >> --- >> meson.build | 2 +- >> include/qemu/target-info.h | 14 +++++ >> target-info.c | 117 +++++++++++++++++++++++++++++++++++++ >> 3 files changed, 132 insertions(+), 1 deletion(-) > > >> +bool target_mips(void) > > I know this is the same lowercase name, but maybe we could consider > directly using target_mips32() instead of keeping the technical debt > of having TARGET_MIPS defined for both 32 and 64-bit targets. > Thankfully we cleared that with recent targets (i.e. LoongArch or > RISC-V -- AVR is a bit different, since 8-bit AVR and AVR32 are > distinct architectures). > > For x86 we often use 'x86' as any of (i386, x86_64, amd64), maybe > we can introduce target_x86() too. > >> +{ >> +#ifdef TARGET_MIPS >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_mips64(void) >> +{ >> +#ifdef TARGET_MIPS64 >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_loongarch64(void) >> +{ >> +#ifdef TARGET_LOONGARCH64 >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_riscv32(void) >> +{ >> +#ifdef TARGET_RISCV32 >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_riscv64(void) >> +{ >> +#ifdef TARGET_RISCV64 >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_ppc(void) > > Ditto, target_ppc32()? > >> +{ >> +#ifdef TARGET_PPC >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_ppc64(void) >> +{ >> +#ifdef TARGET_ppc64 >> + return true; >> +#else >> + return false; >> +#endif >> +} >> + >> +bool target_has_kvm(void) >> +{ >> +#ifdef CONFIG_KVM >> + return true; >> +#else >> + return false; >> +#endif >> +} > I simply tried to reflect existing TARGET_* (so there is no TARGET_PPC32, which is incoherent with having TARGET_RISCV{,32,64}). For the long term, I think we should aim for a 1-1 mapping with SysEmuTarget instead, which is *coherent*. As well, we'll probably want a way to identify target base architecture, like target_base_arm(), target_base_i386(), ..., which will include 32 and 64 bits variants. Since patches for TargetInfo bringing target_arch() are not there yet, I didn't want to bring all the material for a new bike shed, so I simply followed existing TARGET_*. I hope we can have this whole conversation on another dedicated series, once upstream TargetInfo will contain a target_arch field.