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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id b14-20020aa7870e000000b006e3dbec4e7esm11986302pfo.19.2024.02.23.10.39.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Feb 2024 10:39:33 -0800 (PST) Message-ID: <40f9ea46-9351-42b4-bf70-4713fb476b44@linaro.org> Date: Fri, 23 Feb 2024 08:39:30 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 02/21] target/arm: Add PSTATE.ALLINT Content-Language: en-US To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240223103221.1142518-1-ruanjinjie@huawei.com> <20240223103221.1142518-3-ruanjinjie@huawei.com> From: Richard Henderson In-Reply-To: <20240223103221.1142518-3-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/23/24 00:32, Jinjie Ruan via wrote: > The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts. > > Place this in its own field within ENV, as that will > make it easier to handle ALLINT set/clear. > > With the change to pstate_read/write, exception entry > and return are automatically handled. > > Signed-off-by: Jinjie Ruan > --- > v3: > - Remove ALLINT dump in aarch64_cpu_dump_state(). > - Update the commit message. > --- > target/arm/cpu.h | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 63f31e0d98..f9646dbbfb 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -224,6 +224,7 @@ typedef struct CPUArchState { > * semantics as for AArch32, as described in the comments on each field) > * nRW (also known as M[4]) is kept, inverted, in env->aarch64 > * DAIF (exception masks) are kept in env->daif > + * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint > * BTYPE is kept in env->btype > * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate > @@ -261,6 +262,7 @@ typedef struct CPUArchState { > uint32_t btype; /* BTI branch type. spsr[11:10]. */ > uint64_t daif; /* exception masks, in the bits they are in PSTATE */ > uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ > + uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTATE */ > I still think you should keep this bit in env->pstate. r~