Re: [PATCH 2/7] target/mips: Fix emulation of nanoMips EXTRV_S.H instruction

["Philippe Mathieu-Daudé via" <qemu-devel@nongnu.org>]

On 4/5/22 13:03, Stefan Pejic wrote:
> From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
> nanoMips documentation as opcode[20..16]. It is, however, erroneously
> considered as opcode[25..21] in the current QEMU implementation. In
> function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds
> to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and
> v0_t is by mistake passed to the helper gen_helper_extr_s_h().
> 
> Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h()
> to fix this.
> 

Fixes: 8b3698b294 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/nanomips_translate.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
> index 58ae35a156..9ee4df2135 100644
> --- a/target/mips/tcg/nanomips_translate.c.inc
> +++ b/target/mips/tcg/nanomips_translate.c.inc
> @@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
>           case NM_EXTRV_S_H:
>               check_dsp(ctx);
>               tcg_gen_movi_tl(t0, rd >> 3);
> -            gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
> +            gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
>               gen_store_gpr(t0, ret);
>               break;
>           }