From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CTM6i-0002RX-KE for qemu-devel@nongnu.org; Sun, 14 Nov 2004 10:16:00 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CTM6i-0002RP-BV for qemu-devel@nongnu.org; Sun, 14 Nov 2004 10:16:00 -0500 Received: from [129.104.30.34] (helo=mx1.polytechnique.org) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CTLxs-0003uy-RB for qemu-devel@nongnu.org; Sun, 14 Nov 2004 10:06:53 -0500 Received: from localhost (localhost [127.0.0.1]) by djali.polytechnique.org (Postfix) with ESMTP id CABFE331A5 for ; Sun, 14 Nov 2004 16:06:50 +0100 (CET) Received: from djali.polytechnique.org ([127.0.0.1]) by localhost (localhost [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 29211-01 for ; Sun, 14 Nov 2004 16:06:50 +0100 (CET) Received: from bellard.org (unknown [84.99.204.100]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ssl.polytechnique.org (Postfix) with ESMTP id 64E3D33173 for ; Sun, 14 Nov 2004 16:06:50 +0100 (CET) Message-ID: <41977493.6040906@bellard.org> Date: Sun, 14 Nov 2004 16:06:59 +0100 From: Fabrice Bellard MIME-Version: 1.0 Subject: Re: [Qemu-devel] Final call for help: x86: enter instruction bug: PATCH References: <418288C8.3000501@hispeed.ch> <4194C348.6040008@hispeed.ch> <4197724C.2010507@hispeed.ch> In-Reply-To: <4197724C.2010507@hispeed.ch> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Thank you for the enter bug fix. Your patch has still one bug if the SS segment is 16 bit ('env->segs[R_SS].base + EBP' is not correct). I am making a better fix. Fabrice. Stefan Kisdaroczi wrote: > Hi, > > I have attached a patch which fixes the emulation of the i386 enter > instruction. My Test-App is using the enter levels 1-3 is now working > identical under qemu and a real i386 (checked registers and stack > contens with debugger, 16-Bit Mode). > > Please review. Thank you. > > greetings > kisda > > > ------------------------------------------------------------------------ > > diff -uNrp qemu.orig/target-i386/exec.h qemu/target-i386/exec.h > --- qemu.orig/target-i386/exec.h 2004-11-14 13:43:20.000000000 +0100 > +++ qemu/target-i386/exec.h 2004-11-14 13:47:31.000000000 +0100 > @@ -167,6 +167,7 @@ void helper_divl_EAX_T0(uint32_t eip); > void helper_idivl_EAX_T0(uint32_t eip); > void helper_cmpxchg8b(void); > void helper_cpuid(void); > +void helper_enter_level(uint8_t *dst_ptr, int level, int data32); > void helper_sysenter(void); > void helper_sysexit(void); > void helper_rdtsc(void); > diff -uNrp qemu.orig/target-i386/helper.c qemu/target-i386/helper.c > --- qemu.orig/target-i386/helper.c 2004-11-14 13:43:20.000000000 +0100 > +++ qemu/target-i386/helper.c 2004-11-14 13:47:31.000000000 +0100 > @@ -1068,6 +1068,27 @@ void helper_cpuid(void) > } > } > > +void helper_enter_level( uint8_t *dst_ptr, int level, int data32 ) > +{ > + int ofs = 0; > + uint8_t *src_ptr = env->segs[R_SS].base + EBP; > + > + if (data32) { > + /* 32 bit */ > + while (--level) { > + ofs -= 4; > + stl( dst_ptr + ofs, ldl( src_ptr + ofs ) ); > + } > + } > + else { > + /* 16 bit */ > + while (--level) { > + ofs -= 2; > + stw( dst_ptr + ofs, lduw( src_ptr + ofs ) ); > + } > + } > +} > + > void helper_lldt_T0(void) > { > int selector; > diff -uNrp qemu.orig/target-i386/op.c qemu/target-i386/op.c > --- qemu.orig/target-i386/op.c 2004-11-14 13:43:20.000000000 +0100 > +++ qemu/target-i386/op.c 2004-11-14 13:47:31.000000000 +0100 > @@ -695,6 +695,11 @@ void OPPROTO op_cpuid(void) > helper_cpuid(); > } > > +void OPPROTO op_enter_level(void) > +{ > + helper_enter_level((uint8_t *)A0, PARAM1, PARAM2); > +} > + > void OPPROTO op_sysenter(void) > { > helper_sysenter(); > diff -uNrp qemu.orig/target-i386/translate.c qemu/target-i386/translate.c > --- qemu.orig/target-i386/translate.c 2004-11-14 13:43:20.000000000 +0100 > +++ qemu/target-i386/translate.c 2004-11-14 13:51:57.000000000 +0100 > @@ -1694,11 +1694,10 @@ static void gen_popa(DisasContext *s) > /* XXX: check this */ > static void gen_enter(DisasContext *s, int esp_addend, int level) > { > - int ot, level1, addend, opsize; > + int ot, opsize; > > ot = s->dflag + OT_WORD; > level &= 0x1f; > - level1 = level; > opsize = 2 << s->dflag; > > gen_op_movl_A0_ESP(); > @@ -1712,19 +1711,13 @@ static void gen_enter(DisasContext *s, i > gen_op_mov_TN_reg[OT_LONG][0][R_EBP](); > gen_op_st_T0_A0[ot + s->mem_index](); > if (level) { > - while (level--) { > - gen_op_addl_A0_im(-opsize); > - gen_op_addl_T0_im(-opsize); > - gen_op_st_T0_A0[ot + s->mem_index](); > - } > - gen_op_addl_A0_im(-opsize); > + if (level > 1) > + gen_op_enter_level( level, s->dflag ); > + gen_op_addl_A0_im(-opsize * level); > gen_op_st_T1_A0[ot + s->mem_index](); > } > gen_op_mov_reg_T1[ot][R_EBP](); > - addend = -esp_addend; > - if (level1) > - addend -= opsize * (level1 + 1); > - gen_op_addl_T1_im(addend); > + gen_op_addl_T1_im( -esp_addend + (-opsize * level) ); > gen_op_mov_reg_T1[ot][R_ESP](); > } > > > > ------------------------------------------------------------------------ > > _______________________________________________ > Qemu-devel mailing list > Qemu-devel@nongnu.org > http://lists.nongnu.org/mailman/listinfo/qemu-devel