From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Cs5gQ-0004Bi-GM for qemu-devel@nongnu.org; Fri, 21 Jan 2005 15:47:06 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Cs5gH-00047E-S2 for qemu-devel@nongnu.org; Fri, 21 Jan 2005 15:46:58 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Cs5gH-00046x-Me for qemu-devel@nongnu.org; Fri, 21 Jan 2005 15:46:57 -0500 Received: from [195.250.128.73] (helo=smtp1.vol.cz) by monty-python.gnu.org with esmtp (TLSv1:DES-CBC3-SHA:168) (Exim 4.34) id 1Cs5T2-0005rf-Bq for qemu-devel@nongnu.org; Fri, 21 Jan 2005 15:33:16 -0500 Received: from [10.0.0.2] (prg-v-6-220.static.adsl.vol.cz [62.177.70.220]) by smtp1.vol.cz (8.12.9p2/8.12.9) with ESMTP id j0LKXDDm007013 for ; Fri, 21 Jan 2005 21:33:13 +0100 (CET) (envelope-from xnavara@volny.cz) Message-ID: <41F1670C.2060805@volny.cz> Date: Fri, 21 Jan 2005 21:33:16 +0100 From: Filip Navara MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------020302090607020402000905" Subject: [Qemu-devel] [PATCH] minor x86-64 corrections Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------020302090607020402000905 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by smtp1.vol.cz id j0LKXDDm007013 Changelog: 2005-01-21 Filip Navara * Add support for CR8 register. * Don't throw exception when assigning zero to SS register in 64-bit mode. BTW, the callgate support for x86-64 in long mode is broken. See "AMD64=20 Architecture Programmer=92s Manual Volume 3: General-Purpose and System=20 Instructions", page 90. Anybody cares to fix it? Regards, Filip --------------020302090607020402000905 Content-Type: text/plain; name="qemu-64-1.patch" Content-Disposition: inline; filename="qemu-64-1.patch" Content-Transfer-Encoding: 7bit Index: hw/apic.c =================================================================== RCS file: /cvsroot/qemu/qemu/hw/apic.c,v retrieving revision 1.1 diff -u -r1.1 apic.c --- hw/apic.c 3 Jan 2005 23:27:31 -0000 1.1 +++ hw/apic.c 21 Jan 2005 20:13:30 -0000 @@ -100,6 +100,18 @@ return s->apicbase; } +void cpu_set_apic_tpr(CPUState *env, uint8_t val) +{ + APICState *s = env->apic_state; + s->tpr = val; +} + +uint8_t cpu_get_apic_tpr(CPUState *env) +{ + APICState *s = env->apic_state; + return s->tpr; +} + /* return -1 if no bit is set */ static int get_highest_priority_int(uint32_t *tab) { Index: target-i386/exec.h =================================================================== RCS file: /cvsroot/qemu/qemu/target-i386/exec.h,v retrieving revision 1.20 diff -u -r1.20 exec.h --- target-i386/exec.h 8 Jan 2005 18:58:29 -0000 1.20 +++ target-i386/exec.h 21 Jan 2005 20:23:30 -0000 @@ -167,6 +167,8 @@ void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr); int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, int is_write, int is_user, int is_softmmu); +void cpu_set_apic_tpr(CPUX86State *env, uint8_t val); +uint8_t cpu_get_apic_tpr(CPUX86State *env); void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr); void __hidden cpu_lock(void); Index: target-i386/helper.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-i386/helper.c,v retrieving revision 1.40 diff -u -r1.40 helper.c --- target-i386/helper.c 16 Jan 2005 23:35:43 -0000 1.40 +++ target-i386/helper.c 21 Jan 2005 20:13:30 -0000 @@ -1454,8 +1454,13 @@ selector &= 0xffff; if ((selector & 0xfffc) == 0) { /* null selector case */ - if (seg_reg == R_SS) + if (seg_reg == R_SS) { +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) + return; +#endif raise_exception_err(EXCP0D_GPF, 0); + } cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); } else { @@ -2156,6 +2161,11 @@ case 4: cpu_x86_update_cr4(env, T0); break; +#ifdef TARGET_X86_64 + case 8: + cpu_set_apic_tpr(env, (T0 & 0xf) << 4); + break; +#endif default: env->cr[reg] = T0; break; Index: target-i386/op.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-i386/op.c,v retrieving revision 1.28 diff -u -r1.28 op.c --- target-i386/op.c 9 Jan 2005 00:07:04 -0000 1.28 +++ target-i386/op.c 21 Jan 2005 20:13:30 -0000 @@ -1198,6 +1198,11 @@ helper_movl_crN_T0(PARAM1); } +void OPPROTO op_movtl_T0_cr7(void) +{ + T0 = (cpu_get_apic_tpr(env) & 0xf) >> 4; +} + /* DR registers access */ void OPPROTO op_movl_drN_T0(void) { Index: target-i386/translate.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-i386/translate.c,v retrieving revision 1.41 diff -u -r1.41 translate.c --- target-i386/translate.c 16 Jan 2005 01:07:28 -0000 1.41 +++ target-i386/translate.c 21 Jan 2005 20:13:30 -0000 @@ -5641,7 +5641,19 @@ gen_op_mov_reg_T0[ot][rm](); } break; - /* XXX: add CR8 for x86_64 */ +#ifdef TARGET_X86_64 + case 8: + if (b & 2) { + gen_op_mov_TN_reg[ot][0][rm](); + gen_op_movl_crN_T0(reg); + gen_jmp_im(s->pc - s->cs_base); + gen_eob(s); + } else { + gen_op_movtl_T0_cr7(); + gen_op_mov_reg_T0[ot][rm](); + } + break; +#endif default: goto illegal_op; } --------------020302090607020402000905--