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Message-ID: <41F177D2.6040809@bellard.org>
Date: Fri, 21 Jan 2005 22:44:50 +0100
From: Fabrice Bellard <fabrice@bellard.org>
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Subject: Re: [Qemu-devel] [PATCH] minor x86-64 corrections
References: <41F1670C.2060805@volny.cz>
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To: qemu-devel@nongnu.org

Filip Navara wrote:
> Changelog:
>=20
> 2005-01-21 Filip Navara <navaraf@reactos.com>
>=20
> * Add support for CR8 register.
> * Don't throw exception when assigning zero to SS register
> in 64-bit mode.
>=20
> BTW, the callgate support for x86-64 in long mode is broken. See "AMD64=
=20
> Architecture Programmer=92s Manual Volume 3: General-Purpose and System=
=20
> Instructions", page 90. Anybody cares to fix it?

No time yet. It would be interesting to find the problem for the Linux=20
user code too.

> --- target-i386/helper.c	16 Jan 2005 23:35:43 -0000	1.40
> +++ target-i386/helper.c	21 Jan 2005 20:13:30 -0000
> @@ -1454,8 +1454,13 @@
>      selector &=3D 0xffff;
>      if ((selector & 0xfffc) =3D=3D 0) {
>          /* null selector case */
> -        if (seg_reg =3D=3D R_SS)
> +        if (seg_reg =3D=3D R_SS) {
> +#ifdef TARGET_X86_64
> +            if (env->hflags & HF_CS64_MASK)
> +                return;
> +#endif
>              raise_exception_err(EXCP0D_GPF, 0);
> +        }
>          cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);

Maybe the SS segment cache should be set to zero ?

> +void OPPROTO op_movtl_T0_cr7(void)
> +{
> +    T0 =3D (cpu_get_apic_tpr(env) & 0xf) >> 4;
> +}

Why do you call it cr7 ?

Fabrice.