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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b479d90edfsm111825685a.61.2024.11.20.08.10.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Nov 2024 08:10:52 -0800 (PST) Message-ID: <41a67d4e-f7b8-4586-8d52-c32df400b675@redhat.com> Date: Wed, 20 Nov 2024 17:10:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes Content-Language: en-US To: Shameerali Kolothum Thodi , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> <20241108125242.60136-5-shameerali.kolothum.thodi@huawei.com> <1dcea5ca-806f-4f51-8b13-faf5d62eb086@redhat.com> <48bb0455-7c2e-4cc6-aa15-ebe4311d8430@redhat.com> <0803ec1a010a46b9811543e1044c3176@huawei.com> <30ff8ac9ee9b4012aa6962c86ac06375@huawei.com> From: Eric Auger In-Reply-To: <30ff8ac9ee9b4012aa6962c86ac06375@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.143, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 11/20/24 15:16, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: Monday, November 18, 2024 6:10 PM >> To: Shameerali Kolothum Thodi >> ; qemu-arm@nongnu.org; >> qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com; >> ddutile@redhat.com; Linuxarm ; Wangzhou (B) >> ; jiangkunkun ; >> Jonathan Cameron ; >> zhangfei.gao@linaro.org >> Subject: Re: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with >> multiple SMMU nodes > [...] > >>> I think the above won't affect the basic case where I have only one >>> pcie-pxb/SMMUv3. But even in that case hot add seems not working. >>> >>> I tried hacking the min/max ranges as suspected by Nicolin. But still not >> enough to >>> get it working. Do you have any hint on why the hot add(described >> below) is not >>> working? >> Hum thought the duplicate idmap could be the cause. Otherwise I have no >> clue. I would advice to fix it first. > I think I have an idea why the hot add was not working. > > When we have the PCIe topology as something like below, > > -device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \ > -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1 \ > -device pcie-root-port,id=pcie.port2,bus=pcie.1,chassis=2 \ > -device arm-smmuv3-nested,id=smmuv1,pci-bus=pcie.1 \ > ... > > The current IORT generation includes the pcie-root-port dev ids also > in the SMMUv3 node idmaps. > > Hence, when Guest kernel loads, pcieport is also behind the SMMUv3. > > [ 1.466670] pcieport 0000:64:00.0: Adding to iommu group 1 > ... > [ 1.448205] pcieport 0000:64:01.0: Adding to iommu group 2 But it should be the same without multi-instantiation, no? I would have expected this as normal. Has you tested hot-plug without the series laterly? Do you have the same pb? Thanks Eric > > > So when we do a hot add, > device_add vfio-pci,host=0000:75:00.1,bus=pcie.port1,iommufd=iommufd0 > > The Qemu hotplug event handler tries to inject an IRQ to the Guest pcieport > by retrieving the MSI address it is configured with. > > hotplug_event_notify() > msix_prepare_message(): [address: 0xfffff040] > msix_notify() > > The ITS address retrieved here is actually the SMMUv3 translated iova addr, > not the Guest PA. So Guest never sees/receives the interrupt. > > I did hack the IORT code to exclude the pcie-root-port dev ids from the SMMUv3 > node idmaps and the hot add seems to work fine. > > Looks like we need to find all the pcie-root-port dev ids associated with a > SMMUv3/pxb-pcie and exclude them from SMMUv3 node idmaps to get > the hot add working. > > I am not sure though this will create any other issues in IOMMU isolation criteria > (ACS etc,), especially if we want to access the device in Guest user space( I hope > not). > > Thanks, > Shameer > > > >