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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e23d29bb9esm4295644f8f.4.2025.09.05.02.40.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Sep 2025 02:40:18 -0700 (PDT) Message-ID: <41ceadf1-07de-4c8a-8935-d709ac7cf6bc@redhat.com> Date: Fri, 5 Sep 2025 11:40:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 09/15] hw/arm/smmuv3-accel: Support nested STE install/uninstall support Content-Language: en-US To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, skolothumtho@nvidia.com Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, shameerkolothum@gmail.com References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> <20250714155941.22176-10-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250714155941.22176-10-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 7/14/25 5:59 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > Allocates a s1 HWPT for the Guest s1 stage and attaches that > to the dev. This will be invoked when Guest issues dev: I think you shall be more precise because there are so many now ;-) > SMMU_CMD_CFGI_STE/STE_RANGE. > > While at it, we are also exporting both smmu_find_ste() and > smmuv3_flush_config() from smmuv3.c for use here. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 130 +++++++++++++++++++++++++++++++++++++++ > hw/arm/smmuv3-accel.h | 17 +++++ > hw/arm/smmuv3-internal.h | 4 ++ > hw/arm/smmuv3.c | 8 ++- > hw/arm/trace-events | 1 + > 5 files changed, 157 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index fe90d48675..74bf20cfaf 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -18,9 +18,139 @@ > > #include "smmuv3-accel.h" > > +#include "smmuv3-internal.h" > + > #define SMMU_STE_VALID (1ULL << 0) > #define SMMU_STE_CFG_BYPASS (1ULL << 3) > > +static void > +smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool abort) > +{ > + HostIOMMUDeviceIOMMUFD *idev = accel_dev->idev; > + SMMUS1Hwpt *s1_hwpt = accel_dev->s1_hwpt; > + uint32_t hwpt_id; > + > + if (!s1_hwpt || !accel_dev->viommu) { > + return; > + } > + > + if (abort) { > + hwpt_id = accel_dev->viommu->abort_hwpt_id; > + } else { > + hwpt_id = accel_dev->viommu->bypass_hwpt_id; > + } > + > + host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, &error_abort); > + iommufd_backend_free_id(s1_hwpt->iommufd, s1_hwpt->hwpt_id); > + accel_dev->s1_hwpt = NULL; > + g_free(s1_hwpt); > +} > + > +static int > +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev, > + uint32_t data_type, uint32_t data_len, > + void *data) > +{ > + SMMUViommu *viommu = accel_dev->viommu; > + SMMUS1Hwpt *s1_hwpt = accel_dev->s1_hwpt; > + HostIOMMUDeviceIOMMUFD *idev = accel_dev->idev; > + uint32_t flags = 0; > + > + if (!idev || !viommu) { > + return -ENOENT; > + } > + > + if (s1_hwpt) { > + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, true); > + } > + > + s1_hwpt = g_new0(SMMUS1Hwpt, 1); > + s1_hwpt->iommufd = idev->iommufd; > + iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, > + viommu->core.viommu_id, flags, data_type, > + data_len, data, &s1_hwpt->hwpt_id, &error_abort); > + host_iommu_device_iommufd_attach_hwpt(idev, s1_hwpt->hwpt_id, &error_abort); We don't want error_abort here in the prospect to support hotplug. Also I think you should properly cascade any error through Error handles, at least on the install path > + accel_dev->s1_hwpt = s1_hwpt; > + return 0; > +} > + > +void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int sid) return bool and pass Error handle > +{ > + SMMUv3AccelDevice *accel_dev; > + SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid, > + .inval_ste_allowed = true}; > + struct iommu_hwpt_arm_smmuv3 nested_data = {}; > + uint32_t config; > + STE ste; > + int ret; > + > + if (!bs->accel) { > + return; > + } > + > + accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev); > + if (!accel_dev->viommu) { > + return; > + } > + > + ret = smmu_find_ste(sdev->smmu, sid, &ste, &event); > + if (ret) { > + error_report("failed to find STE for sid 0x%x", sid); > + return; > + } > + > + config = STE_CONFIG(&ste); > + if (!STE_VALID(&ste) || !STE_CFG_S1_ENABLED(config)) { > + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, STE_CFG_ABORT(config)); > + smmuv3_flush_config(sdev); > + return; > + } > + > + nested_data.ste[0] = (uint64_t)ste.word[0] | (uint64_t)ste.word[1] << 32; > + nested_data.ste[1] = (uint64_t)ste.word[2] | (uint64_t)ste.word[3] << 32; > + /* V | CONFIG | S1FMT | S1CTXPTR | S1CDMAX */ use bitmasks here and below? > + nested_data.ste[0] &= 0xf80fffffffffffffULL; > + /* S1DSS | S1CIR | S1COR | S1CSH | S1STALLD | EATS */ > + nested_data.ste[1] &= 0x380000ffULL; > + ret = smmuv3_accel_dev_install_nested_ste(accel_dev, > + IOMMU_HWPT_DATA_ARM_SMMUV3, > + sizeof(nested_data), > + &nested_data); > + if (ret) { > + error_report("Unable to install nested STE=%16LX:%16LX, sid=0x%x," > + "ret=%d", nested_data.ste[1], nested_data.ste[0], > + sid, ret); error_setg everywhere > + } > + > + trace_smmuv3_accel_install_nested_ste(sid, nested_data.ste[1], > + nested_data.ste[0]); > +} > + > +static void > +smmuv3_accel_ste_range(gpointer key, gpointer value, gpointer user_data) > +{ > + SMMUDevice *sdev = (SMMUDevice *)key; > + uint32_t sid = smmu_get_sid(sdev); > + SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data; > + > + if (sid >= sid_range->start && sid <= sid_range->end) { > + SMMUv3State *s = sdev->smmu; > + SMMUState *bs = &s->smmu_state; > + > + smmuv3_accel_install_nested_ste(bs, sdev, sid); > + } > +} > + > +void > +smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) > +{ > + if (!bs->accel) { > + return; > + } > + > + g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range); > +} > + > static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *sbus, > PCIBus *bus, int devfn) > { > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index 55a6a353fc..06e81b630d 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -29,10 +29,16 @@ typedef struct SMMUViommu { > QLIST_HEAD(, SMMUv3AccelDevice) device_list; > } SMMUViommu; > > +typedef struct SMMUS1Hwpt { > + IOMMUFDBackend *iommufd; > + uint32_t hwpt_id; > +} SMMUS1Hwpt; > + > typedef struct SMMUv3AccelDevice { > SMMUDevice sdev; > AddressSpace as_sysmem; > HostIOMMUDeviceIOMMUFD *idev; > + SMMUS1Hwpt *s1_hwpt; > SMMUViommu *viommu; > QLIST_ENTRY(SMMUv3AccelDevice) next; > } SMMUv3AccelDevice; > @@ -45,10 +51,21 @@ typedef struct SMMUv3AccelState { > > #if defined(CONFIG_ARM_SMMUV3) && defined(CONFIG_IOMMUFD) > void smmuv3_accel_init(SMMUv3State *s); > +void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int sid); > +void smmuv3_accel_install_nested_ste_range(SMMUState *bs, > + SMMUSIDRange *range); to me should return an int or bool and convey Error handle > #else > static inline void smmuv3_accel_init(SMMUv3State *d) > { > } > +static inline void > +smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int sid) > +{ > +} > +static inline void > +smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) > +{ > +} > #endif > > #endif /* HW_ARM_SMMUV3_ACCEL_H */ > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index b6b7399347..738061c6ad 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -547,6 +547,10 @@ typedef struct CD { > uint32_t word[16]; > } CD; > > +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > + SMMUEventInfo *event); > +void smmuv3_flush_config(SMMUDevice *sdev); > + > /* STE fields */ > > #define STE_VALID(x) extract32((x)->word[0], 0, 1) > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 2f5a8157dd..c94bfe6564 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -630,8 +630,8 @@ bad_ste: > * Supports linear and 2-level stream table > * Return 0 on success, -EINVAL otherwise > */ > -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > - SMMUEventInfo *event) > +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > + SMMUEventInfo *event) > { > dma_addr_t addr, strtab_base; > uint32_t log2size; > @@ -900,7 +900,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev, SMMUEventInfo *event) > return cfg; > } > > -static void smmuv3_flush_config(SMMUDevice *sdev) > +void smmuv3_flush_config(SMMUDevice *sdev) > { > SMMUv3State *s = sdev->smmu; > SMMUState *bc = &s->smmu_state; > @@ -1342,6 +1342,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > > trace_smmuv3_cmdq_cfgi_ste(sid); > smmuv3_flush_config(sdev); > + smmuv3_accel_install_nested_ste(bs, sdev, sid); > > break; > } > @@ -1361,6 +1362,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > sid_range.end = sid_range.start + mask; > > trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end); > + smmuv3_accel_install_nested_ste_range(bs, &sid_range); > smmu_configs_inv_sid_range(bs, sid_range); > break; > } > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index c4537ca1d6..7d232ca17c 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -69,6 +69,7 @@ smmu_reset_exit(void) "" > #smmuv3-accel.c > smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=0x%x (sid=0x%x)" > smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=0x%x (sid=0x%x" > +smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste_0) "sid=%d ste=%"PRIx64":%"PRIx64 > > # strongarm.c > strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" Thanks Eric