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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb9e1bd14sm29341444f8f.28.2025.10.01.09.38.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Oct 2025 09:38:31 -0700 (PDT) Message-ID: <41e361a0-5b61-4731-b12f-9a42b34b50e2@redhat.com> Date: Wed, 1 Oct 2025 18:38:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/27] hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints with iommufd Content-Language: en-US To: Shameer Kolothum , Jonathan Cameron Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , "shameerkolothum@gmail.com" References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-7-skolothumtho@nvidia.com> <20250929170839.00002db9@huawei.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.518, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/30/25 10:03 AM, Shameer Kolothum wrote: > >> -----Original Message----- >> From: Jonathan Cameron >> Sent: 29 September 2025 17:09 >> To: Shameer Kolothum >> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; >> eric.auger@redhat.com; peter.maydell@linaro.org; Jason Gunthorpe >> ; Nicolin Chen ; ddutile@redhat.com; >> berrange@redhat.com; Nathan Chen ; Matt Ochs >> ; smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; zhangfei.gao@linaro.org; >> zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> shameerkolothum@gmail.com >> Subject: Re: [PATCH v4 06/27] hw/arm/smmuv3-accel: Restrict accelerated >> SMMUv3 to vfio-pci endpoints with iommufd >> >> External email: Use caution opening links or attachments >> >> >> On Mon, 29 Sep 2025 14:36:22 +0100 >> Shameer Kolothum wrote: >> >>> Accelerated SMMUv3 is only useful when the device can take advantage of >>> the host's SMMUv3 in nested mode. To keep things simple and correct, we >>> only allow this feature for vfio-pci endpoint devices that use the iommufd >>> backend. We also allow non-endpoint emulated devices like PCI bridges and >>> root ports, so that users can plug in these vfio-pci devices. We can only >>> enforce this if devices are cold plugged. For hotplug cases, give appropriate >>> warnings. >>> >>> Another reason for this limit is to avoid problems with IOTLB >>> invalidations. Some commands (e.g., CMD_TLBI_NH_ASID) lack an >> associated >>> SID, making it difficult to trace the originating device. If we allowed >>> emulated endpoint devices, QEMU would have to invalidate both its own >>> software IOTLB and the host's hardware IOTLB, which could slow things >>> down. >>> >>> Since vfio-pci devices in nested mode rely on the host SMMUv3's nested >>> translation (S1+S2), their get_address_space() callback must return the >>> system address space so that VFIO core can setup correct S2 mappings >>> for guest RAM. >>> >>> So in short: >>> - vfio-pci devices(with iommufd as backend) return the system address >>> space. >>> - bridges and root ports return the IOMMU address space. >>> >>> Signed-off-by: Shameer Kolothum >> One question that really applies to earlier patch and an even more trivial >> comment on a comment than the earlier ones ;) >> >> Reviewed-by: Jonathan Cameron >> >>> --- >>> hw/arm/smmuv3-accel.c | 68 ++++++++++++++++++++++++++++- >>> hw/pci-bridge/pci_expander_bridge.c | 1 - >>> include/hw/pci/pci_bridge.h | 1 + >>> 3 files changed, 68 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c >>> index 79f1713be6..44410cfb2a 100644 >>> --- a/hw/arm/smmuv3-accel.c >>> +++ b/hw/arm/smmuv3-accel.c >>> static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void >> *opaque, >> >> I should have noticed this in previous patch... >> What does add stand for here? This name is not particularly clear to me. > Good question ๐Ÿ˜Š. > > I believe the name comes from the smmu-common.c implementation of > get_address_space: > > static const PCIIOMMUOps smmu_ops = { > .get_address_space = smmu_find_add_as, > }; > Looking at it again, that version allocates a new MR and creates a > new address space per sdev, so perhaps "add" referred to the address > space creation. this stems from the original terminology used in intel-iommu.c (vtd_find_add_as) the smmu-common code looks for a registered device corresponding to @bus and @devfn (this is the 'find'). If it exists it returns it, otherwise it allocates a bus and SMMUDevice object according to what exists and initializes the AddressSpace (this is the 'add'). > > This callback here originally did something similar but no longer does. I don't get why it does not do something similar anymore? > So, I think itโ€™s better to just rename it to smmuv3_accel_get_as() Well I would prefer we keep the original terminology to match other viommu code. Except of course if I misunderstood the existing code. Thanks Eric > > Thanks, > Shameer