From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B0AEC25B78 for ; Tue, 28 May 2024 07:03:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBqrJ-0004Wx-An; Tue, 28 May 2024 03:02:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBqrG-0004Vi-2B; Tue, 28 May 2024 03:02:55 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBqrD-00046x-7Z; Tue, 28 May 2024 03:02:53 -0400 Received: from mail.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4VpNkY3zhGz4x2L; Tue, 28 May 2024 17:02:45 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4VpNkS0820z4wcR; Tue, 28 May 2024 17:02:39 +1000 (AEST) Message-ID: <41e59fa6-c74d-47c7-ba01-690cfaf7f5f1@kaod.org> Date: Tue, 28 May 2024 09:02:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700 support To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com References: <20240527080231.1576609-1-jamin_lin@aspeedtech.com> <20240527080231.1576609-10-jamin_lin@aspeedtech.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=HxTW=M7=kaod.org=clg@ozlabs.org; helo=mail.ozlabs.org X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/27/24 17:58, Philippe Mathieu-Daudé wrote: > Hi, > > On 27/5/24 10:02, Jamin Lin wrote: >> AST2700 fmc/spi controller's address decoding unit is 64KB >> and only bits [31:16] are used for decoding. Introduce seg_to_reg >> and reg_to_seg handlers for ast2700 fmc/spi controller. >> In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. >> >> Signed-off-by: Troy Lee >> Signed-off-by: Jamin Lin >> Reviewed-by: Cédric Le Goater >> --- >>   hw/ssi/aspeed_smc.c | 222 +++++++++++++++++++++++++++++++++++++++++++- >>   1 file changed, 220 insertions(+), 2 deletions(-) >> >> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c >> index df0c63469c..b4006c8339 100644 >> --- a/hw/ssi/aspeed_smc.c >> +++ b/hw/ssi/aspeed_smc.c >> @@ -185,7 +185,7 @@ >>    *   0: 4 bytes >>    *   0x1FFFFFC: 32M bytes >>    * >> - * DMA length is from 1 byte to 32MB (AST2600, AST10x0) >> + * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700) >>    *   0: 1 byte >>    *   0x1FFFFFF: 32M bytes >>    */ >> @@ -670,7 +670,7 @@ static const MemoryRegionOps aspeed_smc_flash_ops = { >>       .endianness = DEVICE_LITTLE_ENDIAN, >>       .valid = { >>           .min_access_size = 1, >> -        .max_access_size = 4, >> +        .max_access_size = 8, > > Is this a bugfix? If so, please use a separate patch. Otherwise > please mention why it is OK to widen access for AST2600 & AST10x0. Ah I missed that. I wonder how we could set different access width tough on the model ? Should we allocate a MemoryRegionOps in the realize() handler and set the width depending on the SoC ? Thanks, C.