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From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 02/10] target/i386: give CC_OP_POPCNT low bits corresponding to MO_TL
Date: Thu, 20 Jun 2024 08:10:37 -0700	[thread overview]
Message-ID: <41ef1b35-f3cc-471f-b84a-ae90b31432da@linaro.org> (raw)
In-Reply-To: <20240620095419.386958-3-pbonzini@redhat.com>

On 6/20/24 02:54, Paolo Bonzini wrote:
> Handle it like the other arithmetic cc_ops.  This simplifies a
> bit the implementation of bit test instructions.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target/i386/cpu.h           | 13 +++++++++++--
>   target/i386/tcg/translate.c |  3 +--
>   2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index f54cd93b3f9..8504a7998fd 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1275,6 +1275,7 @@ typedef enum {
>       CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
>       CC_OP_ADOX, /* CC_SRC2 = O, CC_SRC = rest.  */
>       CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
> +    CC_OP_CLR, /* Z and P set, all other flags clear.  */
>   
>       CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
>       CC_OP_MULW,
> @@ -1331,8 +1332,16 @@ typedef enum {
>       CC_OP_BMILGL,
>       CC_OP_BMILGQ,
>   
> -    CC_OP_CLR, /* Z set, all other flags clear.  */
> -    CC_OP_POPCNT, /* Z via CC_DST, all other flags clear.  */
> +    /*
> +     * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
> +     * is used or implemented, because the translation needs
> +     * to zero-extend CC_DST anyway.
> +     */
> +    CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear.  */
> +    CC_OP_POPCNTW__,
> +    CC_OP_POPCNTL__,
> +    CC_OP_POPCNTQ__,
> +    CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__,
>   
>       CC_OP_NB,
>   } CCOp;
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index f32cda4e169..934c514e64f 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -1019,8 +1019,6 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
>                                .imm = CC_Z };
>       case CC_OP_CLR:
>           return (CCPrepare) { .cond = TCG_COND_ALWAYS };
> -    case CC_OP_POPCNT:
> -        return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src };

The previous patch needs to have changed this to dst.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


  reply	other threads:[~2024-06-20 15:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-20  9:54 [PATCH 00/10] target/i386: make decoding entirely table based Paolo Bonzini
2024-06-20  9:54 ` [PATCH 01/10] target/i386: use cpu_cc_dst for CC_OP_POPCNT Paolo Bonzini
2024-06-20 15:02   ` Richard Henderson
2024-06-20  9:54 ` [PATCH 02/10] target/i386: give CC_OP_POPCNT low bits corresponding to MO_TL Paolo Bonzini
2024-06-20 15:10   ` Richard Henderson [this message]
2024-06-20  9:54 ` [PATCH 03/10] target/i386: convert bit test instructions to new decoder Paolo Bonzini
2024-06-20 15:22   ` Richard Henderson
2024-06-20  9:54 ` [PATCH 04/10] target/i386: try not to force EFLAGS computation for CC_OP_ADOX/ADCX Paolo Bonzini
2024-06-20 15:56   ` Richard Henderson
2024-06-20  9:54 ` [PATCH 05/10] target/i386: decode address before going back to translate.c Paolo Bonzini
2024-06-20  9:54 ` [PATCH 06/10] target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder Paolo Bonzini
2024-06-20 16:14   ` Richard Henderson
2024-06-20  9:54 ` [PATCH 07/10] target/i386: do not check PREFIX_LOCK in old-style decoder Paolo Bonzini
2024-06-20  9:54 ` [PATCH 08/10] target/i386: list instructions still in translate.c Paolo Bonzini
2024-06-20  9:54 ` [PATCH 09/10] target/i386: assert that cc_op* and pc_save are preserved Paolo Bonzini
2024-06-20  9:54 ` [PATCH 10/10] target/i386: remove gen_ext_tl Paolo Bonzini

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