From: Richard Henderson <richard.henderson@linaro.org>
To: Joel Sing <joel@sing.id.au>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: me@carlosedp.com, palmer@sifive.com, Alistair.Francis@wdc.com,
marco@decred.org
Subject: Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Date: Mon, 17 Jun 2019 16:52:44 -0700 [thread overview]
Message-ID: <41ef5fbf-f438-e60a-2fba-a72e3ad422f9@linaro.org> (raw)
In-Reply-To: <20190616191900.GH61734@hippo.sing.id.au>
On 6/16/19 12:19 PM, Joel Sing wrote:
> + /*
> + * Clear the load reservation, since an SC must fail if there is
> + * an SC to any address, in between an LR and SC pair.
> + */
> + tcg_gen_movi_tl(load_res, 0);
> +
> gen_set_label(l2);
This clear needs to be moved down below label l2.
Otherwise, with lr / sc / sc, the second sc could succeed in error.
FWIW, other targets have used -1 as the "invalid" load reservation, since the
architecture does not require address 0 to be unmapped. This should be quite
visible in M-mode with paging disabled and ram at offset 0. Often, other
targets require alignment for the lr/sc address, though I don't see that for riscv.
r~
next prev parent reply other threads:[~2019-06-17 23:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-16 19:19 [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64 Joel Sing
2019-06-16 20:54 ` no-reply
2019-06-17 23:52 ` Richard Henderson [this message]
2019-06-24 6:42 ` Palmer Dabbelt
2019-06-24 18:08 ` Joel Sing
2019-06-25 15:36 ` Richard Henderson
2019-06-26 6:07 ` Palmer Dabbelt
2019-06-26 7:48 ` Richard Henderson
2019-06-26 8:25 ` Palmer Dabbelt
2019-06-26 8:30 ` Richard Henderson
2019-06-26 8:31 ` Palmer Dabbelt
2019-06-25 15:39 ` Richard Henderson
2019-06-26 6:07 ` Palmer Dabbelt
2019-09-24 18:29 ` Alistair Francis
2019-09-24 20:04 ` Palmer Dabbelt
2019-09-24 23:35 ` Alistair Francis
2019-09-25 1:01 ` Alistair Francis
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