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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id d15sm7668459pjr.47.2021.06.05.13.00.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Jun 2021 13:00:10 -0700 (PDT) Subject: Re: [PATCH v16 75/99] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20210604155312.15902-1-alex.bennee@linaro.org> <20210604155312.15902-76-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <420c1b1e-fc9a-186d-d38e-a8b1482c62ba@linaro.org> Date: Sat, 5 Jun 2021 13:00:08 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210604155312.15902-76-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.59, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Claudio Fontana Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/4/21 8:52 AM, Alex Bennée wrote: > From: Claudio Fontana > > when TARGET_AARCH64 is not defined, it is helpful to make > is_aa64() and arm_el_is_aa64 macros defined to "false". > > This way we can make more code TARGET_AARCH64-only. > > Signed-off-by: Claudio Fontana > Signed-off-by: Alex Bennée > --- > target/arm/cpu.h | 37 ++++++++++++++++++++++++------------- > 1 file changed, 24 insertions(+), 13 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index b9b9bd8b01..8614948543 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1060,6 +1060,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); > void aarch64_sve_change_el(CPUARMState *env, int old_el, > int new_el, bool el0_a64); > > +static inline bool is_a64(CPUARMState *env) > +{ > + return env->aarch64; > +} > + > /* > * SVE registers are encoded in KVM's memory in an endianness-invariant format. > * The byte at offset i from the start of the in-memory representation contains > @@ -1089,7 +1094,10 @@ static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } > static inline void aarch64_sve_change_el(CPUARMState *env, int o, > int n, bool a) > { } > -#endif > + > +#define is_a64(env) ((void)env, false) In theory, parenthesis are required around the env expansion. > +#define arm_el_is_aa64(env, el) ((void)env, (void)el, false) Likewise. Otherwise, Reviewed-by: Richard Henderson r~