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[110.175.13.142]) by smtp.gmail.com with ESMTPSA id u21-20020a62d455000000b0053b2681b0e0sm2081231pfl.39.2022.10.14.12.01.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Oct 2022 12:01:59 -0700 (PDT) Message-ID: <420efade-350d-5566-6522-941c9a16aae2@linaro.org> Date: Sat, 15 Oct 2022 06:01:54 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v5 9/9] target/arm: Enable TARGET_TB_PCREL Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220930220312.135327-1-richard.henderson@linaro.org> <20220930220312.135327-10-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.856, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/15/22 04:49, Peter Maydell wrote: > On Tue, 4 Oct 2022 at 20:27, Richard Henderson > wrote: >> >> On 10/4/22 09:23, Peter Maydell wrote: >>>> @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) >>>> >>>> static void gen_exception_internal_insn(DisasContext *s, int excp) >>>> { >>>> + target_ulong pc_save = s->pc_save; >>>> + >>>> gen_a64_update_pc(s, 0); >>>> gen_exception_internal(excp); >>>> s->base.is_jmp = DISAS_NORETURN; >>>> + s->pc_save = pc_save; >>> >>> What is trashing s->pc_save that we have to work around like this, >>> here and in the other similar changes ? >> >> gen_a64_update_pc trashes pc_save. >> >> Off of the top of my head, I can't remember what conditionally uses exceptions (single >> step?). But the usage pattern that is interesting is >> >> brcond(x, y, L1) >> update_pc(disp1); >> exit-or-exception. >> L1: >> update_pc(disp2); >> exit-or-exception. >> >> where at L1 we should have the same pc_save value as we did at the brcond. Saving and >> restoring around (at least some of) the DISAS_NORETURN points achieves that. > > (I figured it would be easiest to continue this conversation > in this thread rather than breaking it up to reply to the v6 > equivalent patch.) > > I guess it does, but it feels like a weird place to be doing that. > If what we want is "at the label L1 we know the pc_save value > needs to be some specific thing", then shouldn't we > achieve that by setting pc_save to a specific value at that > point? e.g. wrapping gen_set_label() with a function that > does "set the label here, guest PC value is going to be this". > Which should generally be the save_pc value at the point > where you emit the brcond() to this label, right? Maybe you > could even have a little struct that wraps up "TCGLabel* > and the pc_save value associated with a branch to it". > But anyway, I think the less confusing way to handle this is > that the changes to pc_save happen at the label, because that's > where the runtime flow-of-control is already being dealt with. Ok, I'll re-work this. > Also, I think that you need to do something for the case > in translate.c where we call tcg_remove_ops_after() -- > that now needs to fix pc_save back up to the value it had > when we called tcg_last_op(). Yes. > (There is also one of those > in target/i386, I haven't checked whether the i386 pcrel > handling series took care of that.) I'll double-check that case too, thanks. r~