Re: [PATCH 2/2] i386/cpu: Drop incorrect comment for CPUID 0x1E

[Xiaoyao Li <xiaoyao.li@intel.com>]

On 11/18/2025 4:08 PM, Zhao Liu wrote:
> The information (tmul_maxk and tmul_maxn) in CPUID 0x1E.0x0.EBX is
> defined for architecture, not for SPR.
> 
> This is to say, these "hardcoded" values won't change in future. If
> the TMUL component needs to be extended for new palettes, there'll
> likely be the new TMUL instructions, or new types of AMX instructions
> that are _parallel_ to TMUL that operate in particular palettes,
> instead of changing current tmul_maxk and tmul_maxn fields in CPUID
> 0x1E.0x0.EBX.
> 
> Furthermore, the previous attempt [*] to make the 0x1E.0x0.EBX fields
> user-configurable is incorrect and unnecessary.
> 
> Therefore, drop the incorrect and misleading comment.
> 
> [*]: https://lore.kernel.org/qemu-devel/20230106083826.5384-2-lei4.wang@intel.com/
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>

The intent was that when new palette introduced in the future, AMX TMUL 
might be adjusted for better performance. But given that SDM now defines 
it clearly as constant:

   EBX[7:0]  TMUL_MAXK tmul_maxk (rows or columns). Value = 16.
   EBX[23:8] TMUL_MAXN tmul_maxn (column bytes).    Value = 64.

so, it cannot change any more.

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>

> ---
>   target/i386/cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 41d224330d05..0c954202cea8 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8403,7 +8403,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       }
>       case 0x1E: {
> -        /* AMX TMUL, for now hardcoded for Sapphire Rapids */
> +        /* AMX TMUL */
>           *eax = 0;
>           *ebx = 0;
>           *ecx = 0;