From: Eric Auger <eric.auger@redhat.com>
To: Cornelia Huck <cohuck@redhat.com>,
eric.auger.pro@gmail.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, kvmarm@lists.linux.dev,
peter.maydell@linaro.org, richard.henderson@linaro.org,
alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev,
sebott@redhat.com, shameerali.kolothum.thodi@huawei.com,
armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,
jdenemar@redhat.com, agraf@csgraf.de
Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org,
pbonzini@redhat.com
Subject: Re: [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc
Date: Mon, 28 Apr 2025 18:38:04 +0200 [thread overview]
Message-ID: <4218aec4-473e-44cc-9d9b-999e6c9e160b@redhat.com> (raw)
In-Reply-To: <20250409144304.912325-14-cohuck@redhat.com>
On 4/9/25 4:43 PM, Cornelia Huck wrote:
> Generated against Linux 6.14-rc1.
>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
> ---
> target/arm/cpu-sysregs.h.inc | 43 +++++++++++++++++++++++++-----------
> 1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index 6c9f9981cc5d..02aae133eb67 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -1,18 +1,8 @@
> -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
> -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
> -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> -DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> -DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> -DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> -DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> -DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> -DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
> -DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +
> DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
> DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
> DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
> +DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)
> DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
> DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
> DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
> @@ -23,13 +13,40 @@ DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)
> DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)
> DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)
> DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)
> -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
> DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)
> +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
> DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
> DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
> DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
> DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
> DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
> DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
> +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
> +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
> DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
> +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
> +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
> +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2)
> +DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
> +DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
> +DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> +DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> +DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)
> +DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> +DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> +DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
> +DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
> +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0)
> +DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
> +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2)
> +DEF(GMID_EL1, 3, 1, 0, 0, 4)
> +DEF(SMIDR_EL1, 3, 1, 0, 0, 6)
> +DEF(CSSELR_EL1, 3, 2, 0, 0, 0)
> DEF(CTR_EL0, 3, 3, 0, 0, 1)
> +DEF(DCZID_EL0, 3, 3, 0, 0, 7)
> +
next prev parent reply other threads:[~2025-04-28 16:39 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 01/13] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
2025-04-28 14:52 ` Eric Auger
2025-04-29 9:31 ` Cornelia Huck
2025-05-13 15:41 ` Daniel P. Berrangé
2025-05-13 15:56 ` Cornelia Huck
2025-05-13 16:17 ` Daniel P. Berrangé
2025-04-09 14:42 ` [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
2025-04-28 15:00 ` Eric Auger
2025-04-09 14:42 ` [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
2025-04-28 15:39 ` Eric Auger
2025-04-29 9:38 ` Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 05/13] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
2025-04-28 15:56 ` Eric Auger
2025-04-29 9:48 ` Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 07/13] arm/cpu: Store aa64smfr0 " Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 " Cornelia Huck
2025-04-28 16:04 ` Eric Auger
2025-04-29 9:51 ` Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 09/13] arm/cpu: Store id_pfr0/1/2 " Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 10/13] arm/cpu: Store id_dfr0/1 " Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 11/13] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 12/13] arm/cpu: Add sysreg generation scripts Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc Cornelia Huck
2025-04-28 16:38 ` Eric Auger [this message]
2025-04-28 16:43 ` [PATCH for-10.1 v5 00/13] arm: rework id register storage Eric Auger
2025-04-29 10:05 ` Cornelia Huck
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