[Qemu-devel] [PATCH v3 0/4] Added 5 instructions to the tricore target

[Qemu-devel] [PATCH v3 0/4] Added 5 instructions to the tricore target

[peer.adelt]

From: Peer Adelt <peer.adelt@c-lab.de>

This patch set contains 5 new instructions:
 - FTOUZ (converts float to unsigned int, rounds towards zero)
 - MADD.F / MSUB.F (multiplies two floats and adds/subtracts result
                    to/from the third operand)
 - MOV (new variant in RR format - see ISA v1.6 for details)
 - JNE (new variant in SBC format - see ISA v1.6 for details)

v3:
  PATCH 1/4: target-tricore: Added FTOUZ instruction
  - Removed unnecessary cast

  PATCH 2/4: target-tricore: Added MADD.F and MSUB.F instructions
  - Provided correct negation options for float32_muladd()
    instead of negating one of the input arguments
  - Calculate NaN results as required in the datasheet

  PATCH 3/4: target-tricore: Added new MOV instruction variant
  - Removed unnecessary parentheses
  - Used temp register to avoid losing the value of r1
  - Checks that r3+1:r3 for a valid 64 Bit extended register

  PATCH 4/4: target-tricore: Added new JNE instruction variant
  - gen_compute_branch() now calculates the displacement value

v2:
  PATCH 3/4: target-tricore: Added new MOV instruction variant
  - Checks TriCore ISA version requirement

  PATCH 4/4: target-tricore: Added new JNE instruction variant
  - Checks TriCore ISA version requirement


Peer Adelt (4):
  target-tricore: Added FTOUZ instruction
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Added new MOV instruction variant
  target-tricore: Added new JNE instruction variant

 target-tricore/fpu_helper.c      | 77 ++++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.h          |  3 ++
 target-tricore/translate.c       | 42 ++++++++++++++++++++++
 target-tricore/tricore-opcodes.h |  3 ++
 4 files changed, 125 insertions(+)

-- 
2.7.4

[Qemu-devel] [PATCH v3 1/4] target-tricore: Added FTOUZ instruction

[peer.adelt]

From: Peer Adelt <peer.adelt@c-lab.de>

Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.

Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 20 ++++++++++++++++++++
 target-tricore/helper.h     |  1 +
 target-tricore/translate.c  |  3 +++
 3 files changed, 24 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 98fe947..16f274c 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -215,3 +215,23 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
     }
     return (uint32_t)f_result;
 }
+
+uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_arg = make_float32(arg);
+    uint32_t result;
+    int32_t flags;
+
+    result = float32_to_uint32_round_to_zero(f_arg, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags) {
+        if (float32_is_any_nan(f_arg)) {
+            result = 0;
+        }
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+    return result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 9333e16..467c880 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
+DEF_HELPER_2(ftouz, i32, env, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index eb3deac..b888b64 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6698,6 +6698,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_ITOF:
         gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RR_FTOUZ:
+        gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.4

[Qemu-devel] [PATCH v3 2/4] target-tricore: Added MADD.F and MSUB.F instructions

[peer.adelt]

From: Peer Adelt <peer.adelt@c-lab.de>

Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
The result is put in D[c]. All operands are floating-point numbers.

Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
---
 target-tricore/fpu_helper.c | 80 +++++++++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.h     |  2 ++
 target-tricore/translate.c  |  8 +++++
 3 files changed, 90 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 16f274c..a4b0973 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -21,6 +21,7 @@
 #include "cpu.h"
 #include "exec/helper-proto.h"
 
+#define QUIET_NAN 0x7fc00000
 #define ADD_NAN   0x7cf00001
 #define DIV_NAN   0x7fc00008
 #define MUL_NAN   0x7fc00002
@@ -47,6 +48,39 @@ static inline bool f_is_denormal(float32 arg)
     return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);
 }
 
+static inline int f_is_pos_infinity(float32 a)
+{
+    return !float32_is_neg(a) && float32_is_infinity(a);
+}
+
+static inline int f_is_neg_infinity(float32 a)
+{
+    return float32_is_neg(a) && float32_is_infinity(a);
+}
+
+static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2,
+                                           float32 arg3, float32 result)
+{
+    if (float32_is_any_nan(arg1) ||
+        float32_is_any_nan(arg2) ||
+        float32_is_any_nan(arg3)) {
+        return QUIET_NAN;
+    } else if (float32_is_infinity(arg1) && float32_is_zero(arg2)) {
+        return MUL_NAN;
+    } else if (float32_is_zero(arg1) && float32_is_infinity(arg2)) {
+        return MUL_NAN;
+    } else if (((f_is_neg_infinity(arg1) && f_is_neg_infinity(arg2)) ||
+                (f_is_pos_infinity(arg1) && f_is_pos_infinity(arg2))) &&
+                 f_is_neg_infinity(arg3)) {
+        return ADD_NAN;
+    } else if (((f_is_neg_infinity(arg1) && f_is_pos_infinity(arg2)) ||
+                (f_is_pos_infinity(arg1) && f_is_neg_infinity(arg2))) &&
+                 f_is_pos_infinity(arg3)) {
+        return ADD_NAN;
+    }
+    return result;
+}
+
 static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
 {
     uint8_t some_excp = 0;
@@ -159,6 +193,52 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
     return (uint32_t)f_result;
 }
 
+uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1,
+                      uint32_t r2, uint32_t r3)
+{
+    uint32_t flags;
+    float32 arg1 = make_float32(r1);
+    float32 arg2 = make_float32(r2);
+    float32 arg3 = make_float32(r3);
+    float32 f_result;
+
+    f_result = float32_muladd(arg1, arg2, arg3, 0, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags) {
+        if (flags & float_flag_invalid) {
+            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result);
+        }
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+    return (uint32_t)f_result;
+}
+
+uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1,
+                      uint32_t r2, uint32_t r3)
+{
+    uint32_t flags;
+    float32 arg1 = make_float32(r1);
+    float32 arg2 = make_float32(r2);
+    float32 arg3 = make_float32(r3);
+    float32 f_result;
+
+    f_result = float32_muladd(arg1, arg2, arg3, float_muladd_negate_product, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags) {
+        if (flags & float_flag_invalid) {
+            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result);
+        }
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+    return (uint32_t)f_result;
+}
+
 uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
 {
     uint32_t result, flags;
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 467c880..c897a44 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -109,6 +109,8 @@ DEF_HELPER_3(fadd, i32, env, i32, i32)
 DEF_HELPER_3(fsub, i32, env, i32, i32)
 DEF_HELPER_3(fmul, i32, env, i32, i32)
 DEF_HELPER_3(fdiv, i32, env, i32, i32)
+DEF_HELPER_4(fmadd, i32, env, i32, i32, i32)
+DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index b888b64..07b0a8b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7096,6 +7096,14 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RRR_SUB_F:
         gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
         break;
+    case OPC2_32_RRR_MADD_F:
+        gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+                         cpu_gpr_d[r2], cpu_gpr_d[r3]);
+        break;
+    case OPC2_32_RRR_MSUB_F:
+        gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+                         cpu_gpr_d[r2], cpu_gpr_d[r3]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.4

Re: [Qemu-devel] [PATCH v3 2/4] target-tricore: Added MADD.F and MSUB.F instructions

[Bastian Koppelmann]

On 06/07/2016 05:49 PM, peer.adelt@c-lab.de wrote:
> From: Peer Adelt <peer.adelt@c-lab.de>
> 
> Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
> The result is put in D[c]. All operands are floating-point numbers.
> 
> Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
> ---
>  target-tricore/fpu_helper.c | 80 +++++++++++++++++++++++++++++++++++++++++++++
>  target-tricore/helper.h     |  2 ++
>  target-tricore/translate.c  |  8 +++++
>  3 files changed, 90 insertions(+)
> 
> diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
> index 16f274c..a4b0973 100644
> --- a/target-tricore/fpu_helper.c
> +++ b/target-tricore/fpu_helper.c
> @@ -21,6 +21,7 @@
>  #include "cpu.h"
>  #include "exec/helper-proto.h"
>  
> +#define QUIET_NAN 0x7fc00000

Not necessary, see comment below

> +static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2,
> +                                           float32 arg3, float32 result)
> +{
> +    if (float32_is_any_nan(arg1) ||
> +        float32_is_any_nan(arg2) ||
> +        float32_is_any_nan(arg3)) {
> +        return QUIET_NAN;

This case is already handled by softfloat. See
fpu/fpu/softfloat-specialize.h. This has a default quiet_nan value for
TriCore.

> +uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1,
> +                      uint32_t r2, uint32_t r3)
> +{
> +    uint32_t flags;
> +    float32 arg1 = make_float32(r1);
> +    float32 arg2 = make_float32(r2);
> +    float32 arg3 = make_float32(r3);
> +    float32 f_result;
> +
> +    f_result = float32_muladd(arg1, arg2, arg3, 0, &env->fp_status);
> +
> +    flags = f_get_excp_flags(env);
> +    if (flags) {
> +        if (flags & float_flag_invalid) {
> +            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result);

You need to squash argN here. The reference manual squashes argN to zero
if they are denormal. This is done in float32_muladd() through the flag
fp_status->flush_inputs_to_zero. However argN as you use them in
f_maddsub_nan_result() are not.

> +uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1,
> +                      uint32_t r2, uint32_t r3)
> +{
> +    uint32_t flags;
> +    float32 arg1 = make_float32(r1);
> +    float32 arg2 = make_float32(r2);
> +    float32 arg3 = make_float32(r3);
> +    float32 f_result;
> +
> +    f_result = float32_muladd(arg1, arg2, arg3, float_muladd_negate_product, &env->fp_status);
> +
> +    flags = f_get_excp_flags(env);
> +    if (flags) {
> +        if (flags & float_flag_invalid) {
> +            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result);

Likewise.

Cheers,
    Bastian

[Qemu-devel] [PATCH v3 3/4] target-tricore: Added new MOV instruction variant

[peer.adelt]

From: Peer Adelt <peer.adelt@c-lab.de>

Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].

Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
---
 target-tricore/translate.c       | 15 +++++++++++++++
 target-tricore/tricore-opcodes.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 07b0a8b..0e970c6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6034,11 +6034,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
     uint32_t op2;
     int r3, r2, r1;
 
+    TCGv temp;
+
     r3 = MASK_OP_RR_D(ctx->opcode);
     r2 = MASK_OP_RR_S2(ctx->opcode);
     r1 = MASK_OP_RR_S1(ctx->opcode);
     op2 = MASK_OP_RR_OP2(ctx->opcode);
 
+    temp = tcg_temp_new();
+
     switch (op2) {
     case OPC2_32_RR_ABS:
         gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
@@ -6224,6 +6228,16 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_MOV:
         tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
         break;
+    case OPC2_32_RR_MOV_64:
+        if (tricore_feature(env, TRICORE_FEATURE_16)) {
+            CHECK_REG_PAIR(r3);
+            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+            tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+            tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
+        break;
     case OPC2_32_RR_NE:
         tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
                            cpu_gpr_d[r2]);
@@ -6344,6 +6358,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
+    tcg_temp_free(temp);
 }
 
 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index df666b0..78ba338 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1062,6 +1062,7 @@ enum {
     OPC2_32_RR_MIN_H                             = 0x78,
     OPC2_32_RR_MIN_HU                            = 0x79,
     OPC2_32_RR_MOV                               = 0x1f,
+    OPC2_32_RR_MOV_64                            = 0x81,
     OPC2_32_RR_NE                                = 0x11,
     OPC2_32_RR_OR_EQ                             = 0x27,
     OPC2_32_RR_OR_GE                             = 0x2b,
-- 
2.7.4

Re: [Qemu-devel] [PATCH v3 3/4] target-tricore: Added new MOV instruction variant

[Bastian Koppelmann]

On 06/07/2016 05:49 PM, peer.adelt@c-lab.de wrote:
> From: Peer Adelt <peer.adelt@c-lab.de>
> 
> Puts the content of data register D[a] into E[c][63:32] and the
> content of data register D[b] into E[c][31:0].
> 
> Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
> ---
>  target-tricore/translate.c       | 15 +++++++++++++++
>  target-tricore/tricore-opcodes.h |  1 +
>  2 files changed, 16 insertions(+)

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Cheers,
    Bastian

[Qemu-devel] [PATCH v3 4/4] target-tricore: Added new JNE instruction variant

[peer.adelt]

From: Peer Adelt <peer.adelt@c-lab.de>

If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).

Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
---
 target-tricore/translate.c       | 16 ++++++++++++++++
 target-tricore/tricore-opcodes.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 0e970c6..8fb8bf1 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3362,9 +3362,15 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
     case OPC1_16_SBC_JEQ:
         gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
         break;
+    case OPC1_16_SBC_JEQ2:
+        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset + 16);
+        break;
     case OPC1_16_SBC_JNE:
         gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
         break;
+    case OPC1_16_SBC_JNE2:
+        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset + 16);
+        break;
 /* SBRN-format jumps */
     case OPC1_16_SBRN_JZ_T:
         temp = tcg_temp_new();
@@ -4097,6 +4103,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
         const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
         gen_compute_branch(ctx, op1, 0, 0, const16, address);
         break;
+    case OPC1_16_SBC_JEQ2:
+    case OPC1_16_SBC_JNE2:
+        if (tricore_feature(env, TRICORE_FEATURE_16)) {
+            address = MASK_OP_SBC_DISP4(ctx->opcode);
+            const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
+            gen_compute_branch(ctx, op1, 0, 0, const16, address);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
+        break;
 /* SBRN-format */
     case OPC1_16_SBRN_JNZ_T:
     case OPC1_16_SBRN_JZ_T:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 78ba338..08394b8 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -311,6 +311,7 @@ enum {
     OPC1_16_SRR_EQ                                   = 0x3a,
     OPC1_16_SB_J                                     = 0x3c,
     OPC1_16_SBC_JEQ                                  = 0x1e,
+    OPC1_16_SBC_JEQ2                                 = 0x9e,
     OPC1_16_SBR_JEQ                                  = 0x3e,
     OPC1_16_SBR_JGEZ                                 = 0xce,
     OPC1_16_SBR_JGTZ                                 = 0x4e,
@@ -318,6 +319,7 @@ enum {
     OPC1_16_SBR_JLEZ                                 = 0x8e,
     OPC1_16_SBR_JLTZ                                 = 0x0e,
     OPC1_16_SBC_JNE                                  = 0x5e,
+    OPC1_16_SBC_JNE2                                 = 0xde,
     OPC1_16_SBR_JNE                                  = 0x7e,
     OPC1_16_SB_JNZ                                   = 0xee,
     OPC1_16_SBR_JNZ                                  = 0xf6,
-- 
2.7.4

Re: [Qemu-devel] [PATCH v3 4/4] target-tricore: Added new JNE instruction variant

[Bastian Koppelmann]

On 06/07/2016 05:49 PM, peer.adelt@c-lab.de wrote:
> From: Peer Adelt <peer.adelt@c-lab.de>
> 
> If D[15] is != sign_ext(const4) then PC will be set to (PC +
> zero_ext(disp4 + 16)).
> 
> Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
> ---
>  target-tricore/translate.c       | 16 ++++++++++++++++
>  target-tricore/tricore-opcodes.h |  2 ++
>  2 files changed, 18 insertions(+)
> 

Minor nitpick -- the commit message should reflect that you added the
JEQ variant as well. But I could do that when applying it to my
tricore-next tree.

Otherwise:
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Cheers,
    Bastian