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From: weiwei <liweiwei@iscas.ac.cn>
To: Alistair Francis <alistair23@gmail.com>
Cc: liweiwei@iscas.ac.cn, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc
Date: Tue, 25 Oct 2022 15:03:03 +0800	[thread overview]
Message-ID: <42442ea9-fa08-a79b-c8d9-b1641fae3c76@iscas.ac.cn> (raw)
In-Reply-To: <CAKmqyKORk8eDQz-GU0CR9Ch9wmtdB9Fc6EGmPHcgSp9Dsr7bWQ@mail.gmail.com>


On 2022/10/25 11:39, Alistair Francis wrote:
> On Fri, Sep 30, 2022 at 11:28 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> All the check for Zcd instructions have been done in their trans function
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/translate.c | 7 -------
>>   1 file changed, 7 deletions(-)
>>
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 347bc913eb..a55b4a7849 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -1087,13 +1087,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>>                ((opcode & 0xe003) == 0xe000) ||
>>                ((opcode & 0xe003) == 0xe002))) {
>>               gen_exception_illegal(ctx);
>> -        } else if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcd ||
>> -                     ctx->cfg_ptr->ext_zcmp || ctx->cfg_ptr->ext_zcmt) &&
>> -                   (((opcode & 0xe003) == 0x2000) ||
>> -                    ((opcode & 0xe003) == 0x2002) ||
>> -                    ((opcode & 0xe003) == 0xa000) ||
>> -                    ((opcode & 0xe003) == 0xa002))) {
>> -            gen_exception_illegal(ctx);
> It's probably best to never add this in the first place.
>
> Remember that the extension can't be enabled until the last patch, so
> it's ok if we don't support it all in one go
>
> Alistair

OK.  I'll update it in next version.

Regards,

Weiwei Li

>
>>           } else {
>>               ctx->opcode = opcode;
>>               ctx->pc_succ_insn = ctx->base.pc_next + 2;
>> --
>> 2.25.1
>>
>>



  reply	other threads:[~2022-10-25  8:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-30  1:23 [RFC 0/8] support subsets of code size reduction extension Weiwei Li
2022-09-30  1:23 ` [RFC 1/8] target/riscv: add cfg properties for Zc* extension Weiwei Li
2022-10-25  3:14   ` Alistair Francis
2022-09-30  1:23 ` [RFC 2/8] target/riscv: add support for Zca, Zcf and Zcd extension Weiwei Li
2022-09-30  1:23 ` [RFC 3/8] target/riscv: add support for Zcb extension Weiwei Li
2022-09-30  1:23 ` [RFC 4/8] target/riscv: add support for Zcmp extension Weiwei Li
2022-09-30  1:23 ` [RFC 5/8] target/riscv: add support for Zcmt extension Weiwei Li
2022-09-30  1:23 ` [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc Weiwei Li
2022-10-25  3:39   ` Alistair Francis
2022-10-25  7:03     ` weiwei [this message]
2022-09-30  1:23 ` [RFC 7/8] target/riscv: expose properties for Zc* extension Weiwei Li
2022-10-25  3:39   ` Alistair Francis
2022-09-30  1:23 ` [RFC 8/8] disas/riscv.c: add disasm support for Zc* Weiwei Li

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