From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
alistair23@gmail.com, chihmin.chao@sifive.com,
palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
linux-csky@vger.kernel.org, wxy194768@alibaba-inc.com,
qemu-devel@nongnu.org
Subject: Re: [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions
Date: Sat, 7 Mar 2020 09:44:11 -0800 [thread overview]
Message-ID: <4253d616-3d28-c848-d559-86407e4fc313@linaro.org> (raw)
In-Reply-To: <a225d9e7-f7ee-71c4-db90-cc27f25470ed@c-sky.com>
On 3/6/20 8:36 PM, LIU Zhiwei wrote:
> I define fields shared between vector helpers and decode code.
> FIELD(VDATA, MLEN, 0, 8)
> FIELD(VDATA, VM, 8, 1)
> FIELD(VDATA, LMUL, 9, 2)
> FIELD(VDATA, NF， 11， 4）
>
> But I can't find a good place to place the fields. There is not a
> "translate.h" in target/riscv.
> Is cpu.h OK？
Perhaps "internals.h" would be better. About 4 of the targets have one of
these. It keeps things that are not relevant to the actual architecture, only
to the implementation, separate.
r~
next prev parent reply other threads:[~2020-03-07 17:45 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 10:35 [PATCH v4 0/5] target/riscv: support vector extension part 2 LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions LIU Zhiwei
2020-02-27 19:17 ` Richard Henderson
2020-02-28 1:50 ` LIU Zhiwei
2020-02-28 3:33 ` Richard Henderson
2020-02-28 6:16 ` LIU Zhiwei
2020-03-07 4:36 ` LIU Zhiwei
2020-03-07 17:44 ` Richard Henderson [this message]
2020-02-25 10:35 ` [PATCH v4 2/5] target/riscv: add vector " LIU Zhiwei
2020-02-27 19:36 ` Richard Henderson
2020-02-28 2:11 ` LIU Zhiwei
2020-03-07 4:29 ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 3/5] target/riscv: add vector index " LIU Zhiwei
2020-02-27 19:49 ` Richard Henderson
2020-02-28 2:13 ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 4/5] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-02-27 20:03 ` Richard Henderson
2020-02-28 2:17 ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 5/5] target/riscv: add vector amo operations LIU Zhiwei
2020-02-28 5:38 ` Richard Henderson
2020-02-28 9:19 ` LIU Zhiwei
2020-02-28 18:46 ` Richard Henderson
2020-02-29 13:16 ` LIU Zhiwei
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