From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers
Date: Wed, 13 Sep 2017 08:28:28 -0700 [thread overview]
Message-ID: <4262b16c-fd18-b551-a510-30833df414ad@linaro.org> (raw)
In-Reply-To: <d1f97f10-921e-1c50-9407-2007b1cbe169@amsat.org>
On 09/12/2017 11:50 AM, Philippe Mathieu-Daudé wrote:
>>
>> - float64 regs[64];
>> + float64 regs[64] __attribute__((aligned(16)));
>
> I understand this should be aligned to the biggest vector register the host
> support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it correct?
No.
Alignment of 16 is sufficient for "older" vector extensions, like altivec,
which require alignment in load/store insns. But (so far at least) newer
vector extensions with larger vector sizes (AVX2, AVX512, ARM SVE) handle
unaligned load/store operations just fine.
Which means we need not require excessive alignment within the cpu struct.
The rule for this is documented in tcg/tcg-op-gvec.h, iirc.
r~
next prev parent reply other threads:[~2017-09-13 15:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-12 16:24 [Qemu-devel] [PATCH v2 00/16] TCG vectorization and example conversion Richard Henderson
2017-09-12 16:24 ` [Qemu-devel] [PATCH v2 01/16] tcg: Add expanders for out-of-line vector helpers Richard Henderson
2017-09-12 16:24 ` [Qemu-devel] [PATCH v2 02/16] tcg: Add types for host vectors Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 03/16] tcg: Add operations " Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 04/16] tcg: Add tcg_op_supported Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 05/16] tcg: Add INDEX_op_invalid Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 06/16] tcg: Add vector infrastructure and ops for add/sub/logic Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers Richard Henderson
2017-09-12 18:50 ` Philippe Mathieu-Daudé
2017-09-12 20:44 ` Philippe Mathieu-Daudé
2017-09-13 15:28 ` Richard Henderson [this message]
2017-09-12 18:55 ` Peter Maydell
2017-09-12 20:17 ` Philippe Mathieu-Daudé
2017-09-12 20:20 ` Peter Maydell
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 08/16] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 09/16] tcg/i386: Add vector operations Richard Henderson
2017-09-14 16:20 ` Alex Bennée
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 10/16] tcg/aarch64: Fully convert tcg_target_op_def Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 11/16] tcg: Remove tcg_regset_clear Richard Henderson
2017-09-12 18:52 ` Philippe Mathieu-Daudé
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 12/16] tcg: Remove tcg_regset_set Richard Henderson
2017-09-12 18:52 ` Philippe Mathieu-Daudé
2017-09-15 10:21 ` Alex Bennée
2017-09-15 17:03 ` Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 13/16] tcg: Remove tcg_regset_{or, and, andnot, not} Richard Henderson
2017-09-12 18:52 ` Philippe Mathieu-Daudé
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 14/16] tcg: Remove tcg_regset_set32 Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 15/16] tcg: Fix types in tcg_regset_{set, reset}_reg Richard Henderson
2017-09-12 16:25 ` [Qemu-devel] [PATCH v2 16/16] tcg/aarch64: Add vector operations Richard Henderson
2017-09-12 16:40 ` [Qemu-devel] [PATCH v2 00/16] TCG vectorization and example conversion no-reply
2017-09-12 16:52 ` no-reply
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