From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DQ8nk-0002ue-BU for qemu-devel@nongnu.org; Mon, 25 Apr 2005 14:59:24 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DQ8nj-0000vj-Kq for qemu-devel@nongnu.org; Mon, 25 Apr 2005 14:59:23 -0400 Received: from [129.104.30.34] (helo=mx1.polytechnique.org) by monty-python.gnu.org with esmtp (Exim 4.34) id 1DQ8oC-0003Ur-VN for qemu-devel@nongnu.org; Mon, 25 Apr 2005 14:59:53 -0400 Received: from [84.99.204.62] (62.204.99-84.rev.gaoland.net [84.99.204.62]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ssl.polytechnique.org (Postfix) with ESMTP id 0054B3318A for ; Mon, 25 Apr 2005 20:56:19 +0200 (CEST) Message-ID: <426D3DBE.9080307@bellard.org> Date: Mon, 25 Apr 2005 20:58:06 +0200 From: Fabrice Bellard MIME-Version: 1.0 Subject: Re: [Qemu-devel] [patch] option -no-tsc for i386 with speedstep References: <20050425111532.GA2554@dizzy.ath.cx> In-Reply-To: <20050425111532.GA2554@dizzy.ath.cx> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Massimo Dal Zotto wrote: > When qemu runs on an i386 cpu with speedstep enabled the clock of the > guest os is not in sync with the clock on the host os because the > vm_timer used for irq 0 generates interrupts at wrong rate when > the host cpu frequency changes. > > The problem is that the vm_timer uses the rdtsc instruction and the value > of ticks_per_sec, computed at start time, for calculating the expire time > of vm_timers. While ticks_per_sec is constant the values returned by > rdtsc are dependent on the current cpu clock, which is not constant if > speedstep is used. > > The problem can be cleary observed by running "xclock -update 1" in the > guest os and observing how the clock speed varies with the cpu freqency. > > The following patch fixes the problem by adding a new option -no-tsc for > the i386 architecture which can be used to disable rdtsc when running on > a cpu with speedstep enabled. > > The patch works for me but I don't know if this is the best way of fixing > this bug. If anyone has a better suggestion it is welcome. This is not the best way to fix the bug. I see 4 solutions: - Compute ticks_per_sec every n seconds and update the timers accordingly. - Use a virtual cycle counter and update ticks_per_sec dynamically. This solution has the advantage of not needing any precise host timer (= very portable), but it will slow down QEMU a bit. - Use a specific driver to get the time efficiently (= without system call) or to know when the host frequency changes - Disable speedstep or use a CPU for which the rdtsc period does not vary even if the CPU frequency changes (the P4 has this feature if I remember correctly and all well designed CPUs should have such a feature !). Fabrice.