From: Aditya Gupta <adityag@linux.ibm.com>
To: Harsh Prateek Bora <harshpb@linux.ibm.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Sourabh Jain" <sourabhjain@linux.ibm.com>,
"Mahesh J Salgaonkar" <mahesh@linux.ibm.com>,
"Hari Bathini" <hbathini@linux.ibm.com>
Subject: Re: [PATCH 3/7] hw/ppc: Handle stash command in PowerNV SBE
Date: Fri, 14 Mar 2025 00:16:46 +0530 [thread overview]
Message-ID: <427f754c-3f40-47e1-873a-1beb69666506@linux.ibm.com> (raw)
In-Reply-To: <59df1008-2127-4ae4-b8e7-72334c58f12e@linux.ibm.com>
On 11/03/25 10:20, Harsh Prateek Bora wrote:
>
>> <...snip...>
>>
>> --- a/hw/ppc/pnv_sbe.c
>> +++ b/hw/ppc/pnv_sbe.c
>> @@ -82,6 +82,8 @@
>> #define SBE_CONTROL_REG_S0 PPC_BIT(14)
>> #define SBE_CONTROL_REG_S1 PPC_BIT(15)
>> +static uint64_t mpipl_skiboot_base = 0x30000000 /*default
>> SKIBOOT_BASE*/;
>> +
>> static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
>> {
>> val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW
>> do? */
>> @@ -281,6 +283,29 @@ static void do_sbe_msg(PnvSBE *sbe)
>> timer_del(sbe->timer);
>> }
>> break;
>> + case SBE_CMD_STASH_MPIPL_CONFIG:
>> + /* key = sbe->mbox[1] */
>> + switch (sbe->mbox[1]) {
>> + case SBE_STASH_KEY_SKIBOOT_BASE:
>> + mpipl_skiboot_base = sbe->mbox[2];
>> + qemu_log_mask(LOG_UNIMP,
>> + "Stashing skiboot base: 0x%lx\n", mpipl_skiboot_base);
>> +
>> + /*
>> + * Set the response register.
>> + *
>> + * Currently setting the same sequence number in
>> + * response as we got in the request.
>> + */
>> + sbe->mbox[4] = sbe->mbox[0]; /* sequence number */
>> + pnv_sbe_set_host_doorbell(sbe,
>> + sbe->host_doorbell | SBE_HOST_RESPONSE_WAITING);
>> +
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command:
>> 0x%x\n", cmd);
>
> Unimplemented SBE_CMD_STASH_MPIPL_CONFIG key ?
Got it. Thanks for the reword suggestion, will do it.
Thanks,
- Aditya G
>
>> + }
>> + break;
>> default:
>> qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command:
>> 0x%x\n", cmd);
>> }
>> diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
>> index b6b378ad14c7..f6cbcf990ed9 100644
>> --- a/include/hw/ppc/pnv_sbe.h
>> +++ b/include/hw/ppc/pnv_sbe.h
>> @@ -53,4 +53,7 @@ struct PnvSBEClass {
>> const MemoryRegionOps *xscom_mbox_ops;
>> };
>> +/* Helper to access stashed SKIBOOT_BASE */
>> +bool pnv_sbe_mpipl_skiboot_base(void);
>> +
>> #endif /* PPC_PNV_SBE_H */
next prev parent reply other threads:[~2025-03-13 18:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 7:19 [PATCH 0/7] Implement MPIPL for PowerNV Aditya Gupta
2025-02-17 7:19 ` [PATCH 1/7] hw/ppc: Log S0/S1 Interrupt triggers by OPAL Aditya Gupta
2025-03-11 4:38 ` Harsh Prateek Bora
2025-03-13 18:43 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 2/7] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-03-11 4:45 ` Harsh Prateek Bora
2025-03-13 18:45 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 3/7] hw/ppc: Handle stash command in PowerNV SBE Aditya Gupta
2025-03-11 4:50 ` Harsh Prateek Bora
2025-03-13 18:46 ` Aditya Gupta [this message]
2025-02-17 7:19 ` [PATCH 4/7] hw/ppc: Add MDST/MDDT/MDRT table structures and offsets Aditya Gupta
2025-03-11 5:11 ` Harsh Prateek Bora
2025-03-13 18:50 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 5/7] hw/ppc: Preserve Memory Regions as per MDST/MDDT tables Aditya Gupta
2025-03-11 5:18 ` Harsh Prateek Bora
2025-03-13 18:54 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE Aditya Gupta
2025-03-11 5:23 ` Harsh Prateek Bora
2025-03-13 18:56 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 7/7] hw/ppc: Implement MPIPL in PowerNV Aditya Gupta
2025-03-11 5:41 ` Harsh Prateek Bora
2025-03-13 19:00 ` Aditya Gupta
2025-02-27 3:37 ` [PATCH 0/7] Implement MPIPL for PowerNV Nicholas Piggin
2025-02-27 6:23 ` Aditya Gupta
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