From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DWvlj-0002D5-Tx for qemu-devel@nongnu.org; Sat, 14 May 2005 08:29:24 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DWvjK-00013U-BB for qemu-devel@nongnu.org; Sat, 14 May 2005 08:26:54 -0400 Received: from [129.104.30.34] (helo=mx1.polytechnique.org) by monty-python.gnu.org with esmtp (Exim 4.34) id 1DWveT-0003zl-1O for qemu-devel@nongnu.org; Sat, 14 May 2005 08:21:53 -0400 Message-ID: <4285EC1E.4090904@bellard.org> Date: Sat, 14 May 2005 14:16:30 +0200 From: Fabrice Bellard MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: request : qemu-smp as target Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org Blue Swirl wrote: > Hi, > > The architecture used in sparc target (sun4m) supports SMP up to a > maximum of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), > it would be easy to add the missing interprocessor interrupts, per-CPU > counters and atomic instructions. It would also be simple to add the > prom functions for starting/stopping CPUs to Proll. Maybe some days' > work in total. > > Higher level (vl.c, cpu-exec.c) could need more work. Maybe Fabrice can > enlighten us? SMP est definitely possible in QEMU - a few days of work are necessary to add the missing generic support and an x86 implementation... but currently I prefer to work an other topics. Just for your information, some choices need to be made: 1) Do the CPUs share the same translation cache ? 2) The first implementation would use a cycle counter to schedule between CPUs. Is it interesting to go further and to use a host thread for each guest CPU at the expense of more locking overhead ? Fabrice.