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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id a24-20020a1709027d9800b0019460c34839sm3156390plm.185.2023.01.27.10.25.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jan 2023 10:25:07 -0800 (PST) Message-ID: <42cff1f8-a256-bf34-039b-9dacc7e4d755@linaro.org> Date: Fri, 27 Jan 2023 08:25:05 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 4/5] target/tricore: Fix OPC2_32_RRRR_DEXTR Content-Language: en-US To: Bastian Koppelmann , qemu-devel@nongnu.org Cc: anton.kochkov@proton.me References: <20230127120328.2520624-1-kbastian@mail.uni-paderborn.de> <20230127120328.2520624-5-kbastian@mail.uni-paderborn.de> From: Richard Henderson In-Reply-To: <20230127120328.2520624-5-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/27/23 02:03, Bastian Koppelmann wrote: > if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the > right by 32 which is undefined behaviour. In this case the TriCore would > do nothing an just return the higher register cpu_reg_d[r1]. We fixed > that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower > register. > > Signed-off-by: Bastian Koppelmann > --- > target/tricore/translate.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/target/tricore/translate.c b/target/tricore/translate.c > index 62128c6aae..b8e0969079 100644 > --- a/target/tricore/translate.c > +++ b/target/tricore/translate.c > @@ -8245,10 +8245,19 @@ static void decode_rrrr_extract_insert(DisasContext *ctx) > if (r1 == r2) { > tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); > } else { > + TCGv msw = tcg_temp_new(); > + TCGv zero = tcg_const_tl(0); tcg_constant_tl(0), which you then don't need to free at the end. > tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); > + tcg_gen_subfi_tl(msw, 32, tmp_pos); > + tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); > + /* if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined /* * If ... */ > + * behaviour. So check that case here and set the low bits to zero > + * which effectivly returns cpu_gpr_d[r1] > + */ > + tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); > + tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); > + tcg_temp_free(zero); > + tcg_temp_free(msw); Otherwise, Reviewed-by: Richard Henderson r~