* [PATCH 1/3] hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'
2023-10-09 17:14 [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Philippe Mathieu-Daudé
@ 2023-10-09 17:14 ` Philippe Mathieu-Daudé
2023-10-09 17:14 ` [PATCH 2/3] hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h' Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-09 17:14 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Philippe Mathieu-Daudé,
Alex Bennée, Aleksandar Rikalo, Aurelien Jarno, Jiaxun Yang,
Richard Henderson, Huacai Chen
"hw/mips/cpudevs.h" contains declarations which are specific
to the MIPS architecture; it doesn't make sense for these to
be called from a non-MIPS architecture. Move the declarations
to "target/mips/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/mips/cpudevs.h | 14 --------------
target/mips/cpu.h | 4 +++-
hw/mips/cps.c | 1 -
hw/mips/fuloong2e.c | 1 -
hw/mips/jazz.c | 1 -
hw/mips/loongson3_virt.c | 1 -
hw/mips/malta.c | 1 -
hw/mips/mips_int.c | 1 -
hw/mips/mipssim.c | 1 -
target/mips/sysemu/cp0_timer.c | 1 -
target/mips/tcg/sysemu/tlb_helper.c | 1 -
11 files changed, 3 insertions(+), 24 deletions(-)
delete mode 100644 include/hw/mips/cpudevs.h
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
deleted file mode 100644
index f7c9728fa9..0000000000
--- a/include/hw/mips/cpudevs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef HW_MIPS_CPUDEVS_H
-#define HW_MIPS_CPUDEVS_H
-
-#include "target/mips/cpu-qom.h"
-
-/* Definitions for MIPS CPU internal devices. */
-
-/* mips_int.c */
-void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
-
-/* mips_timer.c */
-void cpu_mips_clock_init(MIPSCPU *cpu);
-
-#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 67f8e8b988..fb44defc93 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1345,8 +1345,10 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
#if !defined(CONFIG_USER_ONLY)
-/* mips_int.c */
+/* HW declaration specific to the MIPS target */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
+void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
+void cpu_mips_clock_init(MIPSCPU *cpu);
/* mips_itu.c */
void itc_reconfigure(struct MIPSITUState *tag);
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 2b5269ebf1..b6612c1762 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -24,7 +24,6 @@
#include "hw/mips/mips.h"
#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
-#include "hw/mips/cpudevs.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index c6109633fe..97b2c8ed8e 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -30,7 +30,6 @@
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/bootloader.h"
-#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "hw/loader.h"
#include "hw/ide/pci.h"
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index c32d2b0b0a..86dfe05ea8 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -26,7 +26,6 @@
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
-#include "hw/mips/cpudevs.h"
#include "hw/intc/i8259.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index b74b358874..33eae01eca 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -32,7 +32,6 @@
#include "hw/char/serial.h"
#include "hw/intc/loongson_liointc.h"
#include "hw/mips/mips.h"
-#include "hw/mips/cpudevs.h"
#include "hw/mips/fw_cfg.h"
#include "hw/mips/loongson3_bootp.h"
#include "hw/misc/unimp.h"
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index dac27fad9d..b0110c4da6 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -37,7 +37,6 @@
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/bootloader.h"
-#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "qemu/log.h"
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 73437cd90f..6c32e466a3 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -23,7 +23,6 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "hw/irq.h"
-#include "hw/mips/cpudevs.h"
#include "sysemu/kvm.h"
#include "kvm_mips.h"
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 2f951f7fc6..4f743f37eb 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -30,7 +30,6 @@
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
-#include "hw/mips/cpudevs.h"
#include "hw/char/serial.h"
#include "hw/isa/isa.h"
#include "net/net.h"
diff --git a/target/mips/sysemu/cp0_timer.c b/target/mips/sysemu/cp0_timer.c
index 9d2bcb0dea..62de502caa 100644
--- a/target/mips/sysemu/cp0_timer.c
+++ b/target/mips/sysemu/cp0_timer.c
@@ -22,7 +22,6 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
-#include "hw/mips/cpudevs.h"
#include "qemu/timer.h"
#include "sysemu/kvm.h"
#include "internal.h"
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 7dbc2e24c4..4ede904800 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -24,7 +24,6 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
-#include "hw/mips/cpudevs.h"
#include "exec/helper-proto.h"
/* TLB management */
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
2023-10-09 17:14 [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Philippe Mathieu-Daudé
2023-10-09 17:14 ` [PATCH 1/3] hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h' Philippe Mathieu-Daudé
@ 2023-10-09 17:14 ` Philippe Mathieu-Daudé
2023-10-09 17:14 ` [PATCH 3/3] hw/misc/mips_itu: Make MIPSITUState target agnostic Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-09 17:14 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Philippe Mathieu-Daudé,
Alex Bennée, Aleksandar Rikalo, Aurelien Jarno, Jiaxun Yang,
Richard Henderson, Huacai Chen
We already provide "hw/misc/mips_itu.h" to declare prototype
related to MIPSITUState. Move itc_reconfigure() declaration
there.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/misc/mips_itu.h | 2 ++
target/mips/cpu.h | 3 ---
target/mips/tcg/sysemu/cp0_helper.c | 1 +
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 35218b2d14..a413789151 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -79,4 +79,6 @@ struct MIPSITUState {
/* Get ITC Configuration Tag memory region. */
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
+void itc_reconfigure(struct MIPSITUState *tag);
+
#endif /* MIPS_ITU_H */
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index fb44defc93..5fddceff3a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1350,9 +1350,6 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
void cpu_mips_clock_init(MIPSCPU *cpu);
-/* mips_itu.c */
-void itc_reconfigure(struct MIPSITUState *tag);
-
#endif /* !CONFIG_USER_ONLY */
/* helper.c */
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index 5da1124589..d349548743 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -28,6 +28,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "hw/misc/mips_itu.h"
/* SMP helpers. */
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] hw/misc/mips_itu: Make MIPSITUState target agnostic
2023-10-09 17:14 [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Philippe Mathieu-Daudé
2023-10-09 17:14 ` [PATCH 1/3] hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h' Philippe Mathieu-Daudé
2023-10-09 17:14 ` [PATCH 2/3] hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h' Philippe Mathieu-Daudé
@ 2023-10-09 17:14 ` Philippe Mathieu-Daudé
2023-10-10 16:54 ` [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Richard Henderson
2023-10-16 9:05 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-09 17:14 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Philippe Mathieu-Daudé,
Alex Bennée, Aleksandar Rikalo, Aurelien Jarno, Jiaxun Yang,
Richard Henderson, Huacai Chen
When prototyping a heterogenous machine including the ITU,
we get:
include/hw/misc/mips_itu.h:76:5: error: unknown type name 'MIPSCPU'
MIPSCPU *cpu0;
^
MIPSCPU is declared in the target specific "cpu.h" header,
but we don't want to include it, because "cpu.h" is target
specific and its inclusion taints all files including
"mips_itu.h", which become target specific too. We can
however use the 'ArchCPU *' type in the public header.
By keeping the TYPE_MIPS_CPU QOM type check in the link
property declaration, QOM core code will still check the
property is a correct MIPS CPU.
TYPE_MIPS_ITU is still built per-(MIPS)target, but its header
can now be included by other targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/misc/mips_itu.h | 2 +-
hw/misc/mips_itu.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index a413789151..5caed6cc36 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -73,7 +73,7 @@ struct MIPSITUState {
/* SAAR */
uint64_t *saar;
- MIPSCPU *cpu0;
+ ArchCPU *cpu0;
};
/* Get ITC Configuration Tag memory region. */
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 0eda302db4..5a83ccc4e8 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -532,7 +532,7 @@ static void mips_itu_realize(DeviceState *dev, Error **errp)
return;
}
- env = &s->cpu0->env;
+ env = &MIPS_CPU(s->cpu0)->env;
if (env->saarp) {
s->saar = env->CP0_SAAR;
}
@@ -563,7 +563,7 @@ static Property mips_itu_properties[] = {
ITC_FIFO_NUM_MAX),
DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
ITC_SEMAPH_NUM_MAX),
- DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *),
+ DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
DEFINE_PROP_END_OF_LIST(),
};
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype
2023-10-09 17:14 [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-10-09 17:14 ` [PATCH 3/3] hw/misc/mips_itu: Make MIPSITUState target agnostic Philippe Mathieu-Daudé
@ 2023-10-10 16:54 ` Richard Henderson
2023-10-16 9:05 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2023-10-10 16:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Hervé Poussineau, Alex Bennée, Aleksandar Rikalo,
Aurelien Jarno, Jiaxun Yang, Huacai Chen
On 10/9/23 10:14, Philippe Mathieu-Daudé wrote:
> Prepare few MIPS hardware to be integrated in a
> heterogeneous machine:
> - Restrict MIPS-specific HW declaration to target/mips/
> - Replace MIPSCPU by ArchCPU in common HW
>
> Philippe Mathieu-Daudé (3):
> hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'
> hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
> hw/misc/mips_itu: Make MIPSITUState target agnostic
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype
2023-10-09 17:14 [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-10-10 16:54 ` [PATCH 0/3] hw/mips: Cleanup in preparation of heterogenous prototype Richard Henderson
@ 2023-10-16 9:05 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-16 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Alex Bennée, Aleksandar Rikalo,
Aurelien Jarno, Jiaxun Yang, Richard Henderson, Huacai Chen
On 9/10/23 19:14, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (3):
> hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'
> hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
> hw/misc/mips_itu: Make MIPSITUState target agnostic
Queued to mips-next.
^ permalink raw reply [flat|nested] 6+ messages in thread