From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56761) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fMEV2-00014U-Oi for qemu-devel@nongnu.org; Fri, 25 May 2018 11:19:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fMEUz-0005lJ-I1 for qemu-devel@nongnu.org; Fri, 25 May 2018 11:19:24 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:46647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fMEUz-0005k4-Cn for qemu-devel@nongnu.org; Fri, 25 May 2018 11:19:21 -0400 Received: by mail-pf0-x242.google.com with SMTP id p12-v6so2738029pff.13 for ; Fri, 25 May 2018 08:19:21 -0700 (PDT) References: <1527034517-7851-1-git-send-email-mjc@sifive.com> <1527034517-7851-6-git-send-email-mjc@sifive.com> From: Richard Henderson Message-ID: <431fc9e2-e357-ca34-aaff-30d4f4e36f15@linaro.org> Date: Fri, 25 May 2018 08:19:15 -0700 MIME-Version: 1.0 In-Reply-To: <1527034517-7851-6-git-send-email-mjc@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Clark , qemu-devel@nongnu.org Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Alistair Francis , patches@groups.riscv.org On 05/22/2018 05:14 PM, Michael Clark wrote: > Change the API of riscv_set_local_interrupt to take a > write mask and value to allow setting and clearing of > multiple local interrupts atomically in a single call. > Rename the new function to riscv_cpu_update_mip. > > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Palmer Dabbelt > Cc: Alistair Francis > Signed-off-by: Michael Clark > --- Reviewed-by: Richard Henderson r~