From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: ysato@users.sourceforge.jp
Subject: Re: [Qemu-devel] [PATCH v16 19/23] target/rx: Replace operand with prt_ldmi in disassembler
Date: Tue, 4 Jun 2019 07:37:23 +0200 [thread overview]
Message-ID: <4349ab96-c1fe-d7f2-f28e-1c20afb261bf@redhat.com> (raw)
In-Reply-To: <20190531134315.4109-20-richard.henderson@linaro.org>
On 5/31/19 3:43 PM, Richard Henderson wrote:
> This has consistency with prt_ri(). It loads all data before
> beginning output. It uses exactly one call to prt() to emit
> the full instruction.
>
> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/rx/disas.c | 77 +++++++++++++++++------------------------------
> 1 file changed, 27 insertions(+), 50 deletions(-)
>
> diff --git a/target/rx/disas.c b/target/rx/disas.c
> index 64342537ee..515b365528 100644
> --- a/target/rx/disas.c
> +++ b/target/rx/disas.c
> @@ -135,18 +135,18 @@ static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi)
> sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi));
> }
>
> -static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd)
> +static void prt_ldmi(DisasContext *ctx, const char *insn,
> + int ld, int mi, int rs, int rd)
> {
> static const char sizes[][4] = {".b", ".w", ".l", ".uw", ".ub"};
> char dsp[8];
>
> if (ld < 3) {
> rx_index_addr(ctx, dsp, ld, mi);
> - prt("%s[r%d]%s", dsp, rs, sizes[mi]);
> + prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd);
> } else {
> - prt("r%d", rs);
> + prt("%s\tr%d, r%d", insn, rs, rd);
> }
> - prt(", r%d", rd);
> }
>
> static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd)
> @@ -416,8 +416,7 @@ static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a)
> /* and rs,rd */
> static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a)
> {
> - prt("and\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "and", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -440,8 +439,7 @@ static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a)
> /* or rs,rd */
> static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a)
> {
> - prt("or\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "or", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -463,8 +461,7 @@ static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a)
> /* xor rs,rd */
> static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a)
> {
> - prt("xor\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "xor", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -479,8 +476,7 @@ static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a)
> /* tst rs, rd */
> static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
> {
> - prt("tst\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "tst", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -548,8 +544,7 @@ static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a)
> /* add dsp[rs], rd */
> static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a)
> {
> - prt("add\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "add", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -573,8 +568,7 @@ static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a)
> /* cmp dsp[rs], rs2 */
> static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a)
> {
> - prt("cmp\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "cmp", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -589,8 +583,7 @@ static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a)
> /* sub dsp[rs], rd */
> static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a)
> {
> - prt("sub\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "sub", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -611,8 +604,7 @@ static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a)
> /* sbb dsp[rs], rd */
> static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
> {
> - prt("sbb\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "sbb", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -640,8 +632,7 @@ static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a)
> /* max dsp[rs], rd */
> static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a)
> {
> - prt("max\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "max", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -656,8 +647,7 @@ static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a)
> /* min dsp[rs], rd */
> static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a)
> {
> - prt("max\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "min", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -673,8 +663,7 @@ static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a)
> /* mul dsp[rs], rd */
> static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a)
> {
> - prt("mul\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "mul", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -696,8 +685,7 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
> /* emul dsp[rs], rd */
> static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
> {
> - prt("emul\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "emul", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -712,8 +700,7 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
> /* emulu dsp[rs], rd */
> static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
> {
> - prt("emulu\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "emulu", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -728,8 +715,7 @@ static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a)
> /* div dsp[rs], rd */
> static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a)
> {
> - prt("div\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "div", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -744,8 +730,7 @@ static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a)
> /* divu dsp[rs], rd */
> static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
> {
> - prt("divu\t");
> - operand(ctx, a->ld, a->mi, a->rs, a->rd);
> + prt_ldmi(ctx, "divu", a->ld, a->mi, a->rs, a->rd);
> return true;
> }
>
> @@ -1089,8 +1074,7 @@ static bool trans_FADD_ir(DisasContext *ctx, arg_FADD_ir *a)
> /* fadd rs, rd */
> static bool trans_FADD_mr(DisasContext *ctx, arg_FADD_mr *a)
> {
> - prt("fadd\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "fadd", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1105,8 +1089,7 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir *a)
> /* fcmp rs, rd */
> static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
> {
> - prt("fcmp\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "fcmp", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1121,8 +1104,7 @@ static bool trans_FSUB_ir(DisasContext *ctx, arg_FSUB_ir *a)
> /* fsub rs, rd */
> static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a)
> {
> - prt("fsub\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "fsub", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1130,8 +1112,7 @@ static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a)
> /* ftoi rs, rd */
> static bool trans_FTOI(DisasContext *ctx, arg_FTOI *a)
> {
> - prt("ftoi\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "ftoi", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1146,8 +1127,7 @@ static bool trans_FMUL_ir(DisasContext *ctx, arg_FMUL_ir *a)
> /* fmul rs, rd */
> static bool trans_FMUL_mr(DisasContext *ctx, arg_FMUL_mr *a)
> {
> - prt("fmul\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "fmul", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1162,8 +1142,7 @@ static bool trans_FDIV_ir(DisasContext *ctx, arg_FDIV_ir *a)
> /* fdiv rs, rd */
> static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a)
> {
> - prt("fdiv\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "fdiv", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1171,8 +1150,7 @@ static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a)
> /* round rs, rd */
> static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a)
> {
> - prt("round\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "round", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
> @@ -1180,8 +1158,7 @@ static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a)
> /* itof dsp[rs], rd */
> static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a)
> {
> - prt("itof\t");
> - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> + prt_ldmi(ctx, "itof", a->ld, RX_IM_LONG, a->rs, a->rd);
> return true;
> }
>
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2019-06-04 5:39 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-31 13:42 [Qemu-devel] [PATCH v16 00/23] Add RX architecture Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 01/23] target/rx: TCG translation Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 02/23] target/rx: TCG helper Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 03/23] target/rx: CPU definition Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 04/23] target/rx: RX disassembler Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 05/23] hw/intc: RX62N interrupt controller (ICUa) Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 06/23] hw/timer: RX62N internal timer modules Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 07/23] hw/char: RX62N serial communication interface (SCI) Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 08/23] hw/rx: RX Target hardware definition Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 09/23] qemu/bitops.h: Add extract8 and extract16 Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 10/23] hw/registerfields.h: Add 8bit and 16bit register macros Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 11/23] target/rx: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 12/23] target/rx: Add RX to SysEmuTarget Richard Henderson
2019-06-04 5:32 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 13/23] target/rx: Fix cpu types and names Richard Henderson
2019-05-31 14:23 ` Igor Mammedov
2019-05-31 14:59 ` Richard Henderson
2019-05-31 15:15 ` Igor Mammedov
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 14/23] tests: Add rx to machine-none-test.c Richard Henderson
2019-06-04 5:33 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 15/23] hw/rx: Honor -accel qtest Richard Henderson
2019-06-04 5:34 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 16/23] Add rx-softmmu Richard Henderson
2019-06-04 6:38 ` Philippe Mathieu-Daudé
2019-06-04 14:25 ` Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 17/23] MAINTAINERS: Add RX Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 18/23] target/rx: Disassemble rx_index_addr into a string Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 19/23] target/rx: Replace operand with prt_ldmi in disassembler Richard Henderson
2019-06-04 5:37 ` Philippe Mathieu-Daudé [this message]
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 20/23] target/rx: Use prt_ldmi for XCHG_mr disassembly Richard Henderson
2019-06-04 5:38 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 21/23] target/rx: Emit all disassembly in one prt() Richard Henderson
2019-06-04 5:36 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 22/23] target/rx: Collect all bytes during disassembly Richard Henderson
2019-06-04 5:41 ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 23/23] target/rx: Dump bytes for each insn " Richard Henderson
2019-06-04 5:35 ` Philippe Mathieu-Daudé
2019-05-31 14:12 ` [Qemu-devel] [PATCH v16 00/23] Add RX architecture no-reply
2019-06-04 5:23 ` Philippe Mathieu-Daudé
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