From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Peng Liang" <liangpeng10@huawei.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, drjones@redhat.com,
zhang.zhanghailiang@huawei.com, mst@redhat.com,
cohuck@redhat.com, xiexiangyou@huawei.com, pbonzini@redhat.com
Subject: Re: [RFC 1/9] target/arm: convert isar regs to array
Date: Thu, 13 Aug 2020 09:11:08 -0700 [thread overview]
Message-ID: <43673801-9e9d-b090-c187-d8869433f18b@linaro.org> (raw)
In-Reply-To: <6151cd0a-b3ff-ae68-e843-c6b294b846a8@redhat.com>
On 8/13/20 3:42 AM, Philippe Mathieu-Daudé wrote:
>> struct ARMISARegisters {
>> - uint32_t id_isar0;
>> - uint32_t id_isar1;
>> - uint32_t id_isar2;
>> - uint32_t id_isar3;
>> - uint32_t id_isar4;
>> - uint32_t id_isar5;
>> - uint32_t id_isar6;
>> - uint32_t id_mmfr0;
>> - uint32_t id_mmfr1;
>> - uint32_t id_mmfr2;
>> - uint32_t id_mmfr3;
>> - uint32_t id_mmfr4;
>> - uint32_t mvfr0;
>> - uint32_t mvfr1;
>> - uint32_t mvfr2;
>> - uint32_t id_dfr0;
>> - uint32_t dbgdidr;
>> - uint64_t id_aa64isar0;
>> - uint64_t id_aa64isar1;
>> - uint64_t id_aa64pfr0;
>> - uint64_t id_aa64pfr1;
>> - uint64_t id_aa64mmfr0;
>> - uint64_t id_aa64mmfr1;
>> - uint64_t id_aa64mmfr2;
>> - uint64_t id_aa64dfr0;
>> - uint64_t id_aa64dfr1;
>> + uint64_t regs[ID_MAX];
>> } isar;
>
> Why not simply this?
>
> uint64_t isar[ID_MAX];
Because the ARMISARegisters type is used elsewhere.
r~
next prev parent reply other threads:[~2020-08-13 16:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-13 10:26 [RFC 0/9] Support disable/enable CPU features for AArch64 Peng Liang
2020-08-13 10:26 ` [RFC 1/9] target/arm: convert isar regs to array Peng Liang
2020-08-13 10:42 ` Philippe Mathieu-Daudé
2020-08-13 16:11 ` Richard Henderson [this message]
2020-08-13 10:26 ` [RFC 2/9] target/arm: parse cpu feature related options Peng Liang
2020-08-13 12:21 ` Andrew Jones
2020-08-15 2:19 ` Peng Liang
2020-08-15 6:51 ` Andrew Jones
2020-08-13 10:26 ` [RFC 3/9] target/arm: register CPU features for property Peng Liang
2020-08-13 12:34 ` Andrew Jones
2020-08-13 10:26 ` [RFC 4/9] target/arm: Allow ID registers to synchronize to KVM Peng Liang
2020-08-13 10:26 ` [RFC 5/9] target/arm: introduce CPU feature dependency mechanism Peng Liang
2020-08-13 12:48 ` Andrew Jones
2020-08-15 2:19 ` Peng Liang
2020-08-15 6:59 ` Andrew Jones
2020-08-13 10:26 ` [RFC 6/9] target/arm: introduce KVM_CAP_ARM_CPU_FEATURE Peng Liang
2020-08-13 11:00 ` Cornelia Huck
2020-08-15 2:19 ` Peng Liang
2020-08-13 10:26 ` [RFC 7/9] target/arm: Add CPU features to query-cpu-model-expansion Peng Liang
2020-08-13 12:56 ` Andrew Jones
2020-08-15 2:19 ` Peng Liang
2020-08-15 7:02 ` Andrew Jones
2020-08-13 10:26 ` [RFC 8/9] target/arm: Update ID fields Peng Liang
2020-08-13 10:26 ` [RFC 9/9] target/arm: Add more CPU features Peng Liang
2020-08-13 14:10 ` [RFC 0/9] Support disable/enable CPU features for AArch64 Andrew Jones
2020-08-13 16:30 ` no-reply
2020-08-13 16:34 ` no-reply
2020-08-13 16:38 ` no-reply
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