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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions
Date: Fri, 29 Jan 2021 20:50:16 -1000	[thread overview]
Message-ID: <437b165c-5c9c-fefc-b2fc-3fa6152c36bf@linaro.org> (raw)
In-Reply-To: <CAFEAcA_L-vs8d+EMN3WAy3m8cBqtGtkRgy_6_SYLWGuMDSTFFA@mail.gmail.com>

On 1/29/21 1:20 PM, Peter Maydell wrote:
> On Fri, 29 Jan 2021 at 20:14, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Create symbolic constants for all low-byte-addressable
>> and second-byte-addressable registers.  Create a symbol
>> for the registers that need reserving for softmmu.
>>
>> There is no functional change for 's', as this letter is
>> only used for i386.  The BYTEL name is correct for the
>> action we wish from the constraint.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++--------------------
>>  1 file changed, 20 insertions(+), 20 deletions(-)
>>
>> @@ -226,11 +234,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
>>          break;
>>      case 'q':
>>          /* A register that can be used as a byte operand.  */
>> -        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
>> +        ct->regs |= ALL_BYTEL_REGS;
>>          break;
>>      case 'Q':
>>          /* A register with an addressable second byte (e.g. %ah).  */
>> -        ct->regs = 0xf;
>> +        ct->regs |= ALL_BYTEH_REGS;
>>          break;
>>      case 'r':
>>          /* A general register.  */
>> @@ -247,19 +255,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
>>
>>      case 'L':
>>          /* qemu_ld/st data+address constraint */
>> -        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
>> -#ifdef CONFIG_SOFTMMU
>> -        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
>> -        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
>> -#endif
>> +        ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
>>          break;
>>      case 's':
>>          /* qemu_st8_i32 data constraint */
>> -        ct->regs = 0xf;
>> -#ifdef CONFIG_SOFTMMU
>> -        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
>> -        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
>> -#endif
>> +        ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
>>          break;
> 
> Should these cases really be ORing in these expressions
> rather than just using '=' the way the old code was?
> 
> Otherwise
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

All of the cases should always have been ORd.
In theory, one can combine register constraints,
just like one can combine constant constraints.
Not that it would really make sense for this
specific case.

r~


  reply	other threads:[~2021-01-30  6:51 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-29 20:10 [PATCH v3 00/24] tcg: backend constraints cleanup Richard Henderson
2021-01-29 20:10 ` [PATCH v3 01/24] tcg/tci: Drop L and S constraints Richard Henderson
2021-01-29 20:10 ` [PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs Richard Henderson
2021-01-29 23:16   ` Peter Maydell
2021-01-30  6:47     ` Richard Henderson
2021-01-30  7:15       ` Stefan Weil
2021-01-30  8:55         ` Richard Henderson
2021-01-29 20:10 ` [PATCH v3 03/24] tcg/i386: Move constraint type check to tcg_target_const_match Richard Henderson
2021-01-29 23:16   ` Peter Maydell
2021-01-29 20:10 ` [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions Richard Henderson
2021-01-29 23:20   ` Peter Maydell
2021-01-30  6:50     ` Richard Henderson [this message]
2021-01-29 20:10 ` [PATCH v3 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h Richard Henderson
2021-01-29 23:23   ` Peter Maydell
2021-01-29 20:10 ` [PATCH v3 06/24] tcg/arm: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 07/24] tcg/aarch64: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 08/24] tcg/ppc: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 09/24] tcg/tci: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 10/24] tcg/mips: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 11/24] tcg/riscv: " Richard Henderson
2021-01-29 23:24   ` Peter Maydell
2021-01-29 20:10 ` [PATCH v3 12/24] tcg/s390: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 13/24] tcg/sparc: " Richard Henderson
2021-01-29 23:27   ` Peter Maydell
2021-01-31 20:03   ` Philippe Mathieu-Daudé
2021-01-29 20:10 ` [PATCH v3 14/24] tcg: Remove TCG_TARGET_CON_STR_H Richard Henderson
2021-01-29 20:10 ` [PATCH v3 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h Richard Henderson
2021-01-29 20:10 ` [PATCH v3 16/24] tcg/aarch64: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 17/24] tcg/arm: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 18/24] tcg/mips: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 19/24] tcg/ppc: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 20/24] tcg/riscv: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 21/24] tcg/s390: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 22/24] tcg/sparc: " Richard Henderson
2021-01-29 20:10 ` [PATCH v3 23/24] tcg/tci: " Richard Henderson
2021-01-29 23:30   ` Peter Maydell
2021-01-29 20:10 ` [PATCH v3 24/24] tcg: Remove TCG_TARGET_CON_SET_H Richard Henderson
2021-01-29 20:37 ` [PATCH v3 00/24] tcg: backend constraints cleanup no-reply

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