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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id 34sm11382576pgn.56.2021.01.29.22.50.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Jan 2021 22:50:19 -0800 (PST) Subject: Re: [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions To: Peter Maydell References: <20210129201028.787853-1-richard.henderson@linaro.org> <20210129201028.787853-5-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <437b165c-5c9c-fefc-b2fc-3fa6152c36bf@linaro.org> Date: Fri, 29 Jan 2021 20:50:16 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/29/21 1:20 PM, Peter Maydell wrote: > On Fri, 29 Jan 2021 at 20:14, Richard Henderson > wrote: >> >> Create symbolic constants for all low-byte-addressable >> and second-byte-addressable registers. Create a symbol >> for the registers that need reserving for softmmu. >> >> There is no functional change for 's', as this letter is >> only used for i386. The BYTEL name is correct for the >> action we wish from the constraint. >> >> Signed-off-by: Richard Henderson >> --- >> tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++-------------------- >> 1 file changed, 20 insertions(+), 20 deletions(-) >> >> @@ -226,11 +234,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, >> break; >> case 'q': >> /* A register that can be used as a byte operand. */ >> - ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; >> + ct->regs |= ALL_BYTEL_REGS; >> break; >> case 'Q': >> /* A register with an addressable second byte (e.g. %ah). */ >> - ct->regs = 0xf; >> + ct->regs |= ALL_BYTEH_REGS; >> break; >> case 'r': >> /* A general register. */ >> @@ -247,19 +255,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, >> >> case 'L': >> /* qemu_ld/st data+address constraint */ >> - ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; >> -#ifdef CONFIG_SOFTMMU >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); >> -#endif >> + ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS; >> break; >> case 's': >> /* qemu_st8_i32 data constraint */ >> - ct->regs = 0xf; >> -#ifdef CONFIG_SOFTMMU >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); >> -#endif >> + ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS; >> break; > > Should these cases really be ORing in these expressions > rather than just using '=' the way the old code was? > > Otherwise > Reviewed-by: Peter Maydell All of the cases should always have been ORd. In theory, one can combine register constraints, just like one can combine constant constraints. Not that it would really make sense for this specific case. r~