From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"LIU Zhiwei" <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
Date: Thu, 14 Oct 2021 08:39:32 -0700 [thread overview]
Message-ID: <4386f5cf-71f8-f90c-3cd7-14c8e12c62b2@linaro.org> (raw)
In-Reply-To: <420e773b-ca49-9130-8497-971269f6929c@univ-grenoble-alpes.fr>
On 10/14/21 1:57 AM, Frédéric Pétrot wrote:
>>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>>> index 5724a62bb0..6ab5c6aa58 100644
>>> --- a/target/riscv/translate.c
>>> +++ b/target/riscv/translate.c
>>> @@ -67,7 +67,7 @@ typedef struct DisasContext {
>>> to any system register, which includes CSR_FRM, so we do not have
>>> to reset this known value. */
>>> int frm;
>>> - bool w;
>>> + RISCVMXL ol;
>>
>> Why not directly use the xl?
>
> Hi Zhiwei,
>
> I am not speaking for Richard, but my understanding is that 'ol' is linked to
> the instruction being translated, suffixed by 'w' in rv64 and 'w' and 'd' in
> rv128, while 'xl' is the value in mstatus (or misa) depending on the register
> size of the current execution (mxl, sxl, uxl).
Correct.
r~
next prev parent reply other threads:[~2021-10-14 15:58 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson [this message]
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-15 5:21 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
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