From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v6 12/16] target/riscv: AMO operations always raise store/AMO fault
Date: Thu, 22 Aug 2024 15:13:26 +1000 [thread overview]
Message-ID: <43c01b9f-27a4-43b7-805b-d71509a46dc4@linaro.org> (raw)
In-Reply-To: <ZsaNQcdSJM9lSVoX@debug.ba.rivosinc.com>
On 8/22/24 10:58, Deepak Gupta wrote:
> On Thu, Aug 22, 2024 at 10:43:05AM +1000, Richard Henderson wrote:
>> On 8/22/24 07:50, Deepak Gupta wrote:
>>> @@ -1779,13 +1780,25 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>> env->pc += 4;
>>> return;
>>> case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
>>> + if (always_storeamo) {
>>> + cause = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
>>> + }
>>> + goto load_store_fault;
>>> case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
>>> case RISCV_EXCP_LOAD_ADDR_MIS:
>>> case RISCV_EXCP_STORE_AMO_ADDR_MIS:
>>> case RISCV_EXCP_LOAD_ACCESS_FAULT:
>>> + if (always_storeamo) {
>>> + cause = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
>>> + }
>>> + goto load_store_fault;
>>> case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
>>> case RISCV_EXCP_LOAD_PAGE_FAULT:
>>> case RISCV_EXCP_STORE_PAGE_FAULT:
>>> + if (always_storeamo) {
>>> + cause = RISCV_EXCP_STORE_PAGE_FAULT;
>>> + }
>>> + load_store_fault:
>>
>> These case labels need to be re-sorted;
>
> Yeah it looks ugly but I didn't know what's expected. I'll sort cases.
>
>> you're mising load/store when you're intending to check for load alone.
>
> I didn't get this.
Fall through of various case groups into the storeamo checks.
Only the first RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT case is correct.
>> But perhaps in the end maybe just decode_save_opc(ctx, uw2) is better.
>>
>> I expect gen_cmpxchg also needs updating, though I don't have Zacas to hand.
>
> I prefer decode_save_opc(ctx, uw2) but then
>
> $git grep decode_save_opc | wc -l 38
>
> I can update all these locations but it'll be handful.
That's fine. Let's add the operand and update to pass 0 from existing sites as a separate
patch.
r~
next prev parent reply other threads:[~2024-08-22 5:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 21:49 [PATCH v6 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-21 21:49 ` [PATCH v6 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-22 0:25 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 07/16] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-22 0:27 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-22 0:30 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 12/16] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-22 0:43 ` Richard Henderson
2024-08-22 0:58 ` Deepak Gupta
2024-08-22 5:13 ` Richard Henderson [this message]
2024-08-21 21:50 ` [PATCH v6 13/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-22 0:57 ` Richard Henderson
2024-08-22 1:00 ` Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 14/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 15/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 16/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
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