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[89.14.172.11]) by smtp.gmail.com with ESMTPSA id kj5-20020a170907764500b0074ae59d85a4sm963112ejc.20.2022.09.08.01.39.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Sep 2022 01:39:34 -0700 (PDT) Date: Thu, 08 Sep 2022 08:39:27 +0000 From: Bernhard Beschow To: qemu-devel@nongnu.org CC: =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , =?ISO-8859-1?Q?Herv=E9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" Subject: Re: [PATCH 00/42] Consolidate PIIX south bridges In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> Message-ID: <44084D9F-0465-414D-B545-882DED9BF097@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Am 1=2E September 2022 16:25:31 UTC schrieb Bernhard Beschow : >This series consolidates the implementations of the PIIX3 and PIIX4 south= > >bridges and is an extended version of [1]=2E The motivation is to share a= s much > >code as possible and to bring both device models to feature parity such t= hat > >perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machin= e=2E This > >could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on t= his > >list before=2E > > > >The series is structured as follows: First, PIIX3 is changed to instantia= te > >internal devices itself, like PIIX4 does already=2E Second, PIIX3 gets pr= epared > >for the merge with PIIX4 which includes some fixes, cleanups, and renamin= gs=2E > >Third, the same is done for PIIX4=2E In step four the implementations are= merged=2E > >Since some consolidations could be done easier with merged implementation= s, the > >consolidation continues in step five which concludes the series=2E > > > >One particular challenge in this series was that the PIC of PIIX3 used to= be > >instantiated outside of the south bridge while some sub functions require= a PIC > >with populated qemu_irqs=2E This has been solved by introducing a proxy P= IC which > >furthermore allows PIIX3 to be agnostic towards the virtualization techno= logy > >used (KVM, TCG, Xen)=2E Due to consolidation PIIX4 gained the PIC as well= , > >possibly allowing the Malta board to gain KVM capabilities in the future= =2E > Ping Never mind the comment about Malta=2E I think it supports KVM just fine=2E > > >Another challenge was dealing with optional devices where Peter already g= ave > >advice in [1] which this series implements=2E > > > >An unsolved problem still is PCI interrupt handling=2E The first function= > >passed to pci_bus_irqs() is device-specific while the second one seems > >board-specific=2E This causes both PIIX device models to be coupled to a = > >particular board=2E Any advice how to resolve this would be highly apprea= ciated=2E > > > >Last but not least there might be some opportunity to consolidate VM stat= e > >handling, probably by reusing the one from PIIX3=2E Since I'm not very fa= miliar > >with the requirements I didn't touch it so far=2E > > > >Testing done: > >* make check > >* Boot live CD: > > * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom > >manjaro-kde-21=2E3=2E2-220704-linux515=2Eiso` > > * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom > >manjaro-kde-21=2E3=2E2-220704-linux515=2Eiso` > > > >[1] https://lists=2Enongnu=2Eorg/archive/html/qemu-devel/2022-07/msg02348= =2Ehtml > > > >Bernhard Beschow (42): > > hw/i386/pc: Create DMA controllers in south bridges > > hw/i386/pc: Create RTC controllers in south bridges > > hw/i386/pc: No need for rtc_state to be an out-parameter > > hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 > > south bridge > > hw/isa/piix3: Create USB controller in host device > > hw/isa/piix3: Create power management controller in host device > > hw/intc/i8259: Introduce i8259 proxy "isa-pic" > > hw/isa/piix3: Create ISA PIC in host device > > hw/isa/piix3: Create IDE controller in host device > > hw/isa/piix3: Wire up ACPI interrupt internally > > hw/isa/piix3: Remove extra ';' outside of functions > > hw/isa/piix3: Remove unused include > > hw/isa/piix3: Add size constraints to rcr_ops > > hw/isa/piix3: Modernize reset handling > > hw/isa/piix3: Prefer pci_address_space() over get_system_memory() > > hw/isa/piix3: Allow board to provide PCI interrupt routes > > hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS > > hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 > > hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 > > hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" > > hw/isa/piix3: Rename typedef PIIX3State to PIIXState > > hw/mips/malta: Reuse dev variable > > meson: Fix dependencies of piix4 southbridge > > hw/isa/piix4: Add missing initialization > > hw/isa/piix4: Move pci_ide_create_devs() call to board code > > hw/isa/piix4: Make PIIX4's ACPI and USB functions optional > > hw/isa/piix4: Allow board to provide PCI interrupt routes > > hw/isa/piix4: Remove unused code > > hw/isa/piix4: Use ISA PIC device > > hw/isa/piix4: Reuse struct PIIXState from PIIX3 > > hw/isa/piix4: Rename reset control operations to match PIIX3 > > hw/isa/piix4: Rename wrongly named method > > hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" > > hw/isa/piix3: Merge hw/isa/piix4=2Ec > > hw/isa/piix: Harmonize names of reset control memory regions > > hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 > > hw/isa/piix: Rename functions to be shared for interrupt triggering > > hw/isa/piix: Consolidate IRQ triggering > > hw/isa/piix: Unexport PIIXState > > hw/isa/piix: Share PIIX3 base class with PIIX4 > > hw/isa/piix: Drop the "3" from the PIIX base class > > hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI > > controller > > > > MAINTAINERS | 6 +- > > configs/devices/mips-softmmu/common=2Emak | 3 +- > > hw/i386/Kconfig | 3 +- > > hw/i386/acpi-build=2Ec | 4 +- > > hw/i386/pc=2Ec | 19 +- > > hw/i386/pc_piix=2Ec | 72 +-- > > hw/i386/pc_q35=2Ec | 3 +- > > hw/intc/i8259=2Ec | 27 + > > hw/isa/Kconfig | 14 +- > > hw/isa/lpc_ich9=2Ec | 11 + > > hw/isa/meson=2Ebuild | 3 +- > > hw/isa/piix=2Ec | 669 ++++++++++++++++++++++++= > > hw/isa/piix3=2Ec | 431 --------------- > > hw/isa/piix4=2Ec | 325 ------------ > > hw/mips/malta=2Ec | 34 +- > > include/hw/i386/ich9=2Eh | 2 + > > include/hw/i386/pc=2Eh | 2 +- > > include/hw/intc/i8259=2Eh | 14 + > > include/hw/southbridge/piix=2Eh | 41 +- > > 19 files changed, 823 insertions(+), 860 deletions(-) > > create mode 100644 hw/isa/piix=2Ec > > delete mode 100644 hw/isa/piix3=2Ec > > delete mode 100644 hw/isa/piix4=2Ec > > > >-- > >2=2E37=2E3 > > >