From: Richard Henderson <richard.henderson@linaro.org>
To: Jim MacArthur <jim.macarthur@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2
Date: Sat, 15 Nov 2025 13:17:20 +0100 [thread overview]
Message-ID: <4433fb2c-3815-48a2-a74a-0fc38d736dda@linaro.org> (raw)
In-Reply-To: <20251112092048.450090-3-jim.macarthur@linaro.org>
On 11/12/25 10:17, Jim MacArthur wrote:
> @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> if (cpu_isar_feature(aa64_aie, cpu)) {
> valid_mask |= TCR2_AIE;
> }
> + if (cpu_isar_feature(aa64_asid2, cpu)) {
> + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;
> + }
> value &= valid_mask;
> raw_write(env, ri, value);
> }
These same bits also need to be enabled in tcr2_el2_write.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-11-15 12:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur
2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-11-15 12:12 ` Richard Henderson
2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-11-15 12:17 ` Richard Henderson [this message]
2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-11-15 12:21 ` Richard Henderson
-- strict thread matches above, loose matches on Subject: below --
2025-11-20 12:54 [PATCH v2 0/3] Basic ASID2 Support Jim MacArthur
2025-11-20 12:54 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
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