* [PATCH 0/3] Basic ASID2 support
@ 2025-11-12 9:17 Jim MacArthur
2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jim MacArthur @ 2025-11-12 9:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Jim MacArthur
Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max,
then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change
of ASID still causes a TLB flush.
Jim MacArthur (3):
target/arm: Enable ID_AA64MMFR4_EL1 register.
target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2
tests: Add test for ASID2 and write/read of feature bits
target/arm/cpu-features.h | 7 +++++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/helper.c | 7 +++--
target/arm/tcg/cpu64.c | 4 +++
tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++
5 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/system/asid2.c
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register 2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur @ 2025-11-12 9:17 ` Jim MacArthur 2025-11-15 12:12 ` Richard Henderson 2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur 2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur 2 siblings, 1 reply; 8+ messages in thread From: Jim MacArthur @ 2025-11-12 9:17 UTC (permalink / raw) To: qemu-devel; +Cc: Jim MacArthur Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> --- target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 2bb2861c62..2ba49d8478 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 27ebc6f29b..c20334fa65 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) }, - { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) }, { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register 2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur @ 2025-11-15 12:12 ` Richard Henderson 0 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2025-11-15 12:12 UTC (permalink / raw) To: Jim MacArthur, qemu-devel On 11/12/25 10:17, Jim MacArthur wrote: > Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> > --- > target/arm/cpu-sysregs.h.inc | 1 + > target/arm/helper.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~> > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 2bb2861c62..2ba49d8478 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) > DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) > DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) > DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) > +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) > DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) > DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) > DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 27ebc6f29b..c20334fa65 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) }, > - { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > + { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > - .resetvalue = 0 }, > + .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) }, > { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, > .access = PL1_R, .type = ARM_CP_CONST, ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur 2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur @ 2025-11-12 9:17 ` Jim MacArthur 2025-11-15 12:17 ` Richard Henderson 2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur 2 siblings, 1 reply; 8+ messages in thread From: Jim MacArthur @ 2025-11-12 9:17 UTC (permalink / raw) To: qemu-devel; +Cc: Jim MacArthur This just allows read/write of three feature bits. ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB. Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 3 +++ target/arm/tcg/cpu64.c | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 579fa8f8f4..d56bda9ce0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) +FIELD(ID_AA64MMFR4, ASID2, 8, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0; } +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c20334fa65..b380ade957 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_aie, cpu)) { valid_mask |= TCR2_AIE; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + } value &= valid_mask; raw_write(env, ri, value); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6871956382..ef4c0c8d73 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); + t = GET_IDREG(isar, ID_AA64MMFR4); + t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + t = GET_IDREG(isar, ID_AA64ZFR0); t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur @ 2025-11-15 12:17 ` Richard Henderson 0 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2025-11-15 12:17 UTC (permalink / raw) To: Jim MacArthur, qemu-devel On 11/12/25 10:17, Jim MacArthur wrote: > @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, > if (cpu_isar_feature(aa64_aie, cpu)) { > valid_mask |= TCR2_AIE; > } > + if (cpu_isar_feature(aa64_asid2, cpu)) { > + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; > + } > value &= valid_mask; > raw_write(env, ri, value); > } These same bits also need to be enabled in tcr2_el2_write. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits 2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur 2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur 2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur @ 2025-11-12 9:17 ` Jim MacArthur 2025-11-15 12:21 ` Richard Henderson 2 siblings, 1 reply; 8+ messages in thread From: Jim MacArthur @ 2025-11-12 9:17 UTC (permalink / raw) To: qemu-devel; +Cc: Jim MacArthur Tests ASID2 is present and FNG1, FNG0, and A2 are writable, and read value shows the update. Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> --- tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 tests/tcg/aarch64/system/asid2.c diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/asid2.c new file mode 100644 index 0000000000..53dbdc13cc --- /dev/null +++ b/tests/tcg/aarch64/system/asid2.c @@ -0,0 +1,53 @@ +/* + * ASID2 Feature presence and enabled TCR2_EL1 bits test + * + * Copyright (c) 2025 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <stdint.h> +#include <minilib.h> + +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" +#define TCR2_EL1 "S3_0_C2_C0_3" + +int main() +{ + /* + * Test for presence of ASID2 and three feature bits enabled by it: + * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is + * not enabled and read as the written value if A2 is enabled. + */ + + uint64_t out; + uint64_t idreg; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in = feature_mask; + + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" + : [x1] "=r" (idreg)); + if ((idreg & 0xF00) == 0x100) { + /* ASID2 is enabled */ + } else { + ml_printf("FAIL: ASID2 not present in ID_AA64MMFR4 (%lx)\n", idreg); + return 1; + } + + asm("msr " TCR2_EL1 ", %[x0]\n\t" + "mrs %[x1], " TCR2_EL1 "\n\t" + : [x1] "=r" (out) + : [x0] "r" (in)); + + if ((out & feature_mask) == in) { + ml_printf("OK\n"); + return 0; + } else { + ml_printf("FAIL: read value %lx != written value %lx\n", + out & feature_mask, in); + return 1; + } +} -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits 2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur @ 2025-11-15 12:21 ` Richard Henderson 0 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2025-11-15 12:21 UTC (permalink / raw) To: Jim MacArthur, qemu-devel On 11/12/25 10:17, Jim MacArthur wrote: > + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" > + : [x1] "=r" (idreg)); > + if ((idreg & 0xF00) == 0x100) { This should be != 0, just like in isar_feature_aa64_asid2. r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 0/3] Basic ASID2 Support @ 2025-11-20 12:54 Jim MacArthur 2025-11-20 12:54 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur 0 siblings, 1 reply; 8+ messages in thread From: Jim MacArthur @ 2025-11-20 12:54 UTC (permalink / raw) To: qemu-devel; +Cc: Jim MacArthur In V2, I've addressed two comments from Richard Henderson. Thank you for the review. Changes in v2: - patch 2: - Added FNG1, FNG0, A2 to mask for tcr2_el2_write - patch 3: - Changed test for ASID from "=0x100" to "!= 0" Jim MacArthur (3): target/arm: Enable ID_AA64MMFR4_EL1 register. target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 tests: Add test for ASID2 and write/read of feature bits target/arm/cpu-features.h | 7 +++++ target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 10 ++++-- target/arm/tcg/cpu64.c | 4 +++ tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/system/asid2.c -- 2.43.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 2025-11-20 12:54 [PATCH v2 0/3] Basic ASID2 Support Jim MacArthur @ 2025-11-20 12:54 ` Jim MacArthur 0 siblings, 0 replies; 8+ messages in thread From: Jim MacArthur @ 2025-11-20 12:54 UTC (permalink / raw) To: qemu-devel; +Cc: Jim MacArthur This just allows read/write of three feature bits. ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB. Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 6 ++++++ target/arm/tcg/cpu64.c | 4 ++++ 3 files changed, 17 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 579fa8f8f4..d56bda9ce0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) +FIELD(ID_AA64MMFR4, ASID2, 8, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0; } +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c20334fa65..7812a82bab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_aie, cpu)) { valid_mask |= TCR2_AIE; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + } value &= valid_mask; raw_write(env, ri, value); } @@ -6121,6 +6124,9 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |= TCR2_AMEC0 | TCR2_AMEC1; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + } value &= valid_mask; raw_write(env, ri, value); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6871956382..ef4c0c8d73 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); + t = GET_IDREG(isar, ID_AA64MMFR4); + t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + t = GET_IDREG(isar, ID_AA64ZFR0); t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-11-20 12:59 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur 2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur 2025-11-15 12:12 ` Richard Henderson 2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur 2025-11-15 12:17 ` Richard Henderson 2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur 2025-11-15 12:21 ` Richard Henderson -- strict thread matches above, loose matches on Subject: below -- 2025-11-20 12:54 [PATCH v2 0/3] Basic ASID2 Support Jim MacArthur 2025-11-20 12:54 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
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