* [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:11 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Richard Henderson
` (17 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Re-use the TARGET_PAGE_BITS_VARY mechanism to define
TARGET_PAGE_SIZE and friends when not compiling per-target.
Inline qemu_target_page_{size,mask,bits} as they are now trivial.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
After this, we could in fact remove qemu_target_page_foo(), etc.
We certainly don't need to convert any more uses of TARGET_PAGE_FOO.
r~
---
include/exec/cpu-all.h | 21 +-------------
include/exec/poison.h | 5 ----
include/exec/target_page.h | 58 ++++++++++++++++++++++++++++++++++----
page-target.c | 18 ------------
page-vary-target.c | 2 ++
5 files changed, 55 insertions(+), 49 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 09f537d06f..8f7aebb088 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -105,26 +105,7 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
/* page related stuff */
#include "exec/cpu-defs.h"
-#ifdef TARGET_PAGE_BITS_VARY
-# include "exec/page-vary.h"
-extern const TargetPageBits target_page;
-# ifdef CONFIG_DEBUG_TCG
-# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
- target_page.bits; })
-# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
- (target_long)target_page.mask; })
-# else
-# define TARGET_PAGE_BITS target_page.bits
-# define TARGET_PAGE_MASK ((target_long)target_page.mask)
-# endif
-# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
-#else
-# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
-# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
-# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
-#endif
-
-#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+#include "exec/target_page.h"
CPUArchState *cpu_copy(CPUArchState *env);
diff --git a/include/exec/poison.h b/include/exec/poison.h
index f4283f693a..ce43a12965 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -44,11 +44,6 @@
#pragma GCC poison TARGET_FMT_ld
#pragma GCC poison TARGET_FMT_lu
-#pragma GCC poison TARGET_PAGE_SIZE
-#pragma GCC poison TARGET_PAGE_MASK
-#pragma GCC poison TARGET_PAGE_BITS
-#pragma GCC poison TARGET_PAGE_ALIGN
-
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
#pragma GCC poison CPU_INTERRUPT_HALT
diff --git a/include/exec/target_page.h b/include/exec/target_page.h
index 98ffbb5c23..8e89e5cbe6 100644
--- a/include/exec/target_page.h
+++ b/include/exec/target_page.h
@@ -14,10 +14,56 @@
#ifndef EXEC_TARGET_PAGE_H
#define EXEC_TARGET_PAGE_H
-size_t qemu_target_page_size(void);
-int qemu_target_page_mask(void);
-int qemu_target_page_bits(void);
-int qemu_target_page_bits_min(void);
-
-size_t qemu_target_pages_to_MiB(size_t pages);
+/*
+ * If compiling per-target, get the real values.
+ * For generic code, reuse the mechanism for variable page size.
+ */
+#ifdef COMPILING_PER_TARGET
+#include "cpu-param.h"
+#include "exec/target_long.h"
+#define TARGET_PAGE_TYPE target_long
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_TYPE int
+#endif
+
+#ifdef TARGET_PAGE_BITS_VARY
+# include "exec/page-vary.h"
+extern const TargetPageBits target_page;
+# ifdef CONFIG_DEBUG_TCG
+# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
+ target_page.bits; })
+# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
+ (TARGET_PAGE_TYPE)target_page.mask; })
+# else
+# define TARGET_PAGE_BITS target_page.bits
+# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask)
+# endif
+# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
+#else
+# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
+# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
+# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS)
+#endif
+
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+
+static inline size_t qemu_target_page_size(void)
+{
+ return TARGET_PAGE_SIZE;
+}
+
+static inline int qemu_target_page_mask(void)
+{
+ return TARGET_PAGE_MASK;
+}
+
+static inline int qemu_target_page_bits(void)
+{
+ return TARGET_PAGE_BITS;
+}
+
+int qemu_target_page_bits_min(void);
+size_t qemu_target_pages_to_MiB(size_t pages);
+
#endif
diff --git a/page-target.c b/page-target.c
index 82211c8593..321e43d06f 100644
--- a/page-target.c
+++ b/page-target.c
@@ -8,24 +8,6 @@
#include "qemu/osdep.h"
#include "exec/target_page.h"
-#include "exec/cpu-defs.h"
-#include "cpu.h"
-#include "exec/cpu-all.h"
-
-size_t qemu_target_page_size(void)
-{
- return TARGET_PAGE_SIZE;
-}
-
-int qemu_target_page_mask(void)
-{
- return TARGET_PAGE_MASK;
-}
-
-int qemu_target_page_bits(void)
-{
- return TARGET_PAGE_BITS;
-}
int qemu_target_page_bits_min(void)
{
diff --git a/page-vary-target.c b/page-vary-target.c
index 343b4adb95..1b4a9a10be 100644
--- a/page-vary-target.c
+++ b/page-vary-target.c
@@ -37,5 +37,7 @@ void finalize_target_page_bits(void)
{
#ifdef TARGET_PAGE_BITS_VARY
finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN);
+#else
+ finalize_target_page_bits_common(TARGET_PAGE_BITS);
#endif
}
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h
2025-03-07 18:56 ` [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h Richard Henderson
@ 2025-03-07 19:11 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Re-use the TARGET_PAGE_BITS_VARY mechanism to define
> TARGET_PAGE_SIZE and friends when not compiling per-target.
> Inline qemu_target_page_{size,mask,bits} as they are now trivial.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>
> After this, we could in fact remove qemu_target_page_foo(), etc.
> We certainly don't need to convert any more uses of TARGET_PAGE_FOO.
>
> r~
>
> ---
> include/exec/cpu-all.h | 21 +-------------
> include/exec/poison.h | 5 ----
> include/exec/target_page.h | 58 ++++++++++++++++++++++++++++++++++----
> page-target.c | 18 ------------
> page-vary-target.c | 2 ++
> 5 files changed, 55 insertions(+), 49 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 09f537d06f..8f7aebb088 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -105,26 +105,7 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
>
> /* page related stuff */
> #include "exec/cpu-defs.h"
> -#ifdef TARGET_PAGE_BITS_VARY
> -# include "exec/page-vary.h"
> -extern const TargetPageBits target_page;
> -# ifdef CONFIG_DEBUG_TCG
> -# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
> - target_page.bits; })
> -# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
> - (target_long)target_page.mask; })
> -# else
> -# define TARGET_PAGE_BITS target_page.bits
> -# define TARGET_PAGE_MASK ((target_long)target_page.mask)
> -# endif
> -# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
> -#else
> -# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
> -# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
> -# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
> -#endif
> -
> -#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
> +#include "exec/target_page.h"
>
> CPUArchState *cpu_copy(CPUArchState *env);
>
> diff --git a/include/exec/poison.h b/include/exec/poison.h
> index f4283f693a..ce43a12965 100644
> --- a/include/exec/poison.h
> +++ b/include/exec/poison.h
> @@ -44,11 +44,6 @@
> #pragma GCC poison TARGET_FMT_ld
> #pragma GCC poison TARGET_FMT_lu
>
> -#pragma GCC poison TARGET_PAGE_SIZE
> -#pragma GCC poison TARGET_PAGE_MASK
> -#pragma GCC poison TARGET_PAGE_BITS
> -#pragma GCC poison TARGET_PAGE_ALIGN
> -
> #pragma GCC poison CPU_INTERRUPT_HARD
> #pragma GCC poison CPU_INTERRUPT_EXITTB
> #pragma GCC poison CPU_INTERRUPT_HALT
> diff --git a/include/exec/target_page.h b/include/exec/target_page.h
> index 98ffbb5c23..8e89e5cbe6 100644
> --- a/include/exec/target_page.h
> +++ b/include/exec/target_page.h
> @@ -14,10 +14,56 @@
> #ifndef EXEC_TARGET_PAGE_H
> #define EXEC_TARGET_PAGE_H
>
> -size_t qemu_target_page_size(void);
> -int qemu_target_page_mask(void);
> -int qemu_target_page_bits(void);
> -int qemu_target_page_bits_min(void);
> -
> -size_t qemu_target_pages_to_MiB(size_t pages);
> +/*
> + * If compiling per-target, get the real values.
> + * For generic code, reuse the mechanism for variable page size.
> + */
> +#ifdef COMPILING_PER_TARGET
> +#include "cpu-param.h"
> +#include "exec/target_long.h"
> +#define TARGET_PAGE_TYPE target_long
> +#else
> +#define TARGET_PAGE_BITS_VARY
> +#define TARGET_PAGE_TYPE int
> +#endif
> +
> +#ifdef TARGET_PAGE_BITS_VARY
> +# include "exec/page-vary.h"
> +extern const TargetPageBits target_page;
> +# ifdef CONFIG_DEBUG_TCG
> +# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
> + target_page.bits; })
> +# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
> + (TARGET_PAGE_TYPE)target_page.mask; })
> +# else
> +# define TARGET_PAGE_BITS target_page.bits
> +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask)
> +# endif
> +# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
> +#else
> +# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
> +# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
> +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS)
> +#endif
> +
> +#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
> +
> +static inline size_t qemu_target_page_size(void)
> +{
> + return TARGET_PAGE_SIZE;
> +}
> +
> +static inline int qemu_target_page_mask(void)
> +{
> + return TARGET_PAGE_MASK;
> +}
> +
> +static inline int qemu_target_page_bits(void)
> +{
> + return TARGET_PAGE_BITS;
> +}
> +
> +int qemu_target_page_bits_min(void);
> +size_t qemu_target_pages_to_MiB(size_t pages);
> +
> #endif
> diff --git a/page-target.c b/page-target.c
> index 82211c8593..321e43d06f 100644
> --- a/page-target.c
> +++ b/page-target.c
> @@ -8,24 +8,6 @@
>
> #include "qemu/osdep.h"
> #include "exec/target_page.h"
> -#include "exec/cpu-defs.h"
> -#include "cpu.h"
> -#include "exec/cpu-all.h"
> -
> -size_t qemu_target_page_size(void)
> -{
> - return TARGET_PAGE_SIZE;
> -}
> -
> -int qemu_target_page_mask(void)
> -{
> - return TARGET_PAGE_MASK;
> -}
> -
> -int qemu_target_page_bits(void)
> -{
> - return TARGET_PAGE_BITS;
> -}
>
> int qemu_target_page_bits_min(void)
> {
> diff --git a/page-vary-target.c b/page-vary-target.c
> index 343b4adb95..1b4a9a10be 100644
> --- a/page-vary-target.c
> +++ b/page-vary-target.c
> @@ -37,5 +37,7 @@ void finalize_target_page_bits(void)
> {
> #ifdef TARGET_PAGE_BITS_VARY
> finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN);
> +#else
> + finalize_target_page_bits_common(TARGET_PAGE_BITS);
> #endif
> }
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
2025-03-07 18:56 ` [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:11 ` Pierrick Bouvier
2025-03-07 22:03 ` Philippe Mathieu-Daudé
2025-03-07 18:56 ` [PATCH 02/16] accel/tcg: Compile watchpoint.c once Richard Henderson
` (16 subsequent siblings)
18 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Some of these bits are actually common to all cpus; while the
reset have common reservations for target-specific usage.
While generic code cannot know what the target-specific usage is,
common code can know what to do with the bits, e.g. single-step.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 53 +--------------------------
include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++
include/exec/poison.h | 13 -------
3 files changed, 71 insertions(+), 65 deletions(-)
create mode 100644 include/exec/cpu-interrupt.h
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 8f7aebb088..9e6724097c 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -21,6 +21,7 @@
#include "exec/page-protection.h"
#include "exec/cpu-common.h"
+#include "exec/cpu-interrupt.h"
#include "exec/memory.h"
#include "exec/tswap.h"
#include "hw/core/cpu.h"
@@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
CPUArchState *cpu_copy(CPUArchState *env);
-/* Flags for use in ENV->INTERRUPT_PENDING.
-
- The numbers assigned here are non-sequential in order to preserve
- binary compatibility with the vmstate dump. Bit 0 (0x0001) was
- previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
- the vmstate dump. */
-
-/* External hardware interrupt pending. This is typically used for
- interrupts from devices. */
-#define CPU_INTERRUPT_HARD 0x0002
-
-/* Exit the current TB. This is typically used when some system-level device
- makes some change to the memory mapping. E.g. the a20 line change. */
-#define CPU_INTERRUPT_EXITTB 0x0004
-
-/* Halt the CPU. */
-#define CPU_INTERRUPT_HALT 0x0020
-
-/* Debug event pending. */
-#define CPU_INTERRUPT_DEBUG 0x0080
-
-/* Reset signal. */
-#define CPU_INTERRUPT_RESET 0x0400
-
-/* Several target-specific external hardware interrupts. Each target/cpu.h
- should define proper names based on these defines. */
-#define CPU_INTERRUPT_TGT_EXT_0 0x0008
-#define CPU_INTERRUPT_TGT_EXT_1 0x0010
-#define CPU_INTERRUPT_TGT_EXT_2 0x0040
-#define CPU_INTERRUPT_TGT_EXT_3 0x0200
-#define CPU_INTERRUPT_TGT_EXT_4 0x1000
-
-/* Several target-specific internal interrupts. These differ from the
- preceding target-specific interrupts in that they are intended to
- originate from within the cpu itself, typically in response to some
- instruction being executed. These, therefore, are not masked while
- single-stepping within the debugger. */
-#define CPU_INTERRUPT_TGT_INT_0 0x0100
-#define CPU_INTERRUPT_TGT_INT_1 0x0800
-#define CPU_INTERRUPT_TGT_INT_2 0x2000
-
-/* First unused bit: 0x4000. */
-
-/* The set of all bits that should be masked when single-stepping. */
-#define CPU_INTERRUPT_SSTEP_MASK \
- (CPU_INTERRUPT_HARD \
- | CPU_INTERRUPT_TGT_EXT_0 \
- | CPU_INTERRUPT_TGT_EXT_1 \
- | CPU_INTERRUPT_TGT_EXT_2 \
- | CPU_INTERRUPT_TGT_EXT_3 \
- | CPU_INTERRUPT_TGT_EXT_4)
-
#include "cpu.h"
#ifdef CONFIG_USER_ONLY
diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h
new file mode 100644
index 0000000000..40715193ca
--- /dev/null
+++ b/include/exec/cpu-interrupt.h
@@ -0,0 +1,70 @@
+/*
+ * Flags for use with cpu_interrupt()
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef CPU_INTERRUPT_H
+#define CPU_INTERRUPT_H
+
+/*
+ * The numbers assigned here are non-sequential in order to preserve binary
+ * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
+ * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
+ */
+
+/*
+ * External hardware interrupt pending.
+ * This is typically used for interrupts from devices.
+ */
+#define CPU_INTERRUPT_HARD 0x0002
+
+/*
+ * Exit the current TB. This is typically used when some system-level device
+ * makes some change to the memory mapping. E.g. the a20 line change.
+ */
+#define CPU_INTERRUPT_EXITTB 0x0004
+
+/* Halt the CPU. */
+#define CPU_INTERRUPT_HALT 0x0020
+
+/* Debug event pending. */
+#define CPU_INTERRUPT_DEBUG 0x0080
+
+/* Reset signal. */
+#define CPU_INTERRUPT_RESET 0x0400
+
+/*
+ * Several target-specific external hardware interrupts. Each target/cpu.h
+ * should define proper names based on these defines.
+ */
+#define CPU_INTERRUPT_TGT_EXT_0 0x0008
+#define CPU_INTERRUPT_TGT_EXT_1 0x0010
+#define CPU_INTERRUPT_TGT_EXT_2 0x0040
+#define CPU_INTERRUPT_TGT_EXT_3 0x0200
+#define CPU_INTERRUPT_TGT_EXT_4 0x1000
+
+/*
+ * Several target-specific internal interrupts. These differ from the
+ * preceding target-specific interrupts in that they are intended to
+ * originate from within the cpu itself, typically in response to some
+ * instruction being executed. These, therefore, are not masked while
+ * single-stepping within the debugger.
+ */
+#define CPU_INTERRUPT_TGT_INT_0 0x0100
+#define CPU_INTERRUPT_TGT_INT_1 0x0800
+#define CPU_INTERRUPT_TGT_INT_2 0x2000
+
+/* First unused bit: 0x4000. */
+
+/* The set of all bits that should be masked when single-stepping. */
+#define CPU_INTERRUPT_SSTEP_MASK \
+ (CPU_INTERRUPT_HARD \
+ | CPU_INTERRUPT_TGT_EXT_0 \
+ | CPU_INTERRUPT_TGT_EXT_1 \
+ | CPU_INTERRUPT_TGT_EXT_2 \
+ | CPU_INTERRUPT_TGT_EXT_3 \
+ | CPU_INTERRUPT_TGT_EXT_4)
+
+#endif /* CPU_INTERRUPT_H */
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 35721366d7..8ed04b3108 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -46,19 +46,6 @@
#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
-#pragma GCC poison CPU_INTERRUPT_HARD
-#pragma GCC poison CPU_INTERRUPT_EXITTB
-#pragma GCC poison CPU_INTERRUPT_HALT
-#pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
-
#pragma GCC poison CONFIG_ALPHA_DIS
#pragma GCC poison CONFIG_HPPA_DIS
#pragma GCC poison CONFIG_I386_DIS
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h
2025-03-07 18:56 ` [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Richard Henderson
@ 2025-03-07 19:11 ` Pierrick Bouvier
2025-03-07 22:03 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Some of these bits are actually common to all cpus; while the
> reset have common reservations for target-specific usage.
> While generic code cannot know what the target-specific usage is,
> common code can know what to do with the bits, e.g. single-step.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-all.h | 53 +--------------------------
> include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++
> include/exec/poison.h | 13 -------
> 3 files changed, 71 insertions(+), 65 deletions(-)
> create mode 100644 include/exec/cpu-interrupt.h
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 8f7aebb088..9e6724097c 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -21,6 +21,7 @@
>
> #include "exec/page-protection.h"
> #include "exec/cpu-common.h"
> +#include "exec/cpu-interrupt.h"
> #include "exec/memory.h"
> #include "exec/tswap.h"
> #include "hw/core/cpu.h"
> @@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
>
> CPUArchState *cpu_copy(CPUArchState *env);
>
> -/* Flags for use in ENV->INTERRUPT_PENDING.
> -
> - The numbers assigned here are non-sequential in order to preserve
> - binary compatibility with the vmstate dump. Bit 0 (0x0001) was
> - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
> - the vmstate dump. */
> -
> -/* External hardware interrupt pending. This is typically used for
> - interrupts from devices. */
> -#define CPU_INTERRUPT_HARD 0x0002
> -
> -/* Exit the current TB. This is typically used when some system-level device
> - makes some change to the memory mapping. E.g. the a20 line change. */
> -#define CPU_INTERRUPT_EXITTB 0x0004
> -
> -/* Halt the CPU. */
> -#define CPU_INTERRUPT_HALT 0x0020
> -
> -/* Debug event pending. */
> -#define CPU_INTERRUPT_DEBUG 0x0080
> -
> -/* Reset signal. */
> -#define CPU_INTERRUPT_RESET 0x0400
> -
> -/* Several target-specific external hardware interrupts. Each target/cpu.h
> - should define proper names based on these defines. */
> -#define CPU_INTERRUPT_TGT_EXT_0 0x0008
> -#define CPU_INTERRUPT_TGT_EXT_1 0x0010
> -#define CPU_INTERRUPT_TGT_EXT_2 0x0040
> -#define CPU_INTERRUPT_TGT_EXT_3 0x0200
> -#define CPU_INTERRUPT_TGT_EXT_4 0x1000
> -
> -/* Several target-specific internal interrupts. These differ from the
> - preceding target-specific interrupts in that they are intended to
> - originate from within the cpu itself, typically in response to some
> - instruction being executed. These, therefore, are not masked while
> - single-stepping within the debugger. */
> -#define CPU_INTERRUPT_TGT_INT_0 0x0100
> -#define CPU_INTERRUPT_TGT_INT_1 0x0800
> -#define CPU_INTERRUPT_TGT_INT_2 0x2000
> -
> -/* First unused bit: 0x4000. */
> -
> -/* The set of all bits that should be masked when single-stepping. */
> -#define CPU_INTERRUPT_SSTEP_MASK \
> - (CPU_INTERRUPT_HARD \
> - | CPU_INTERRUPT_TGT_EXT_0 \
> - | CPU_INTERRUPT_TGT_EXT_1 \
> - | CPU_INTERRUPT_TGT_EXT_2 \
> - | CPU_INTERRUPT_TGT_EXT_3 \
> - | CPU_INTERRUPT_TGT_EXT_4)
> -
> #include "cpu.h"
>
> #ifdef CONFIG_USER_ONLY
> diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h
> new file mode 100644
> index 0000000000..40715193ca
> --- /dev/null
> +++ b/include/exec/cpu-interrupt.h
> @@ -0,0 +1,70 @@
> +/*
> + * Flags for use with cpu_interrupt()
> + *
> + * Copyright (c) 2003 Fabrice Bellard
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#ifndef CPU_INTERRUPT_H
> +#define CPU_INTERRUPT_H
> +
> +/*
> + * The numbers assigned here are non-sequential in order to preserve binary
> + * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
> + * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
> + */
> +
> +/*
> + * External hardware interrupt pending.
> + * This is typically used for interrupts from devices.
> + */
> +#define CPU_INTERRUPT_HARD 0x0002
> +
> +/*
> + * Exit the current TB. This is typically used when some system-level device
> + * makes some change to the memory mapping. E.g. the a20 line change.
> + */
> +#define CPU_INTERRUPT_EXITTB 0x0004
> +
> +/* Halt the CPU. */
> +#define CPU_INTERRUPT_HALT 0x0020
> +
> +/* Debug event pending. */
> +#define CPU_INTERRUPT_DEBUG 0x0080
> +
> +/* Reset signal. */
> +#define CPU_INTERRUPT_RESET 0x0400
> +
> +/*
> + * Several target-specific external hardware interrupts. Each target/cpu.h
> + * should define proper names based on these defines.
> + */
> +#define CPU_INTERRUPT_TGT_EXT_0 0x0008
> +#define CPU_INTERRUPT_TGT_EXT_1 0x0010
> +#define CPU_INTERRUPT_TGT_EXT_2 0x0040
> +#define CPU_INTERRUPT_TGT_EXT_3 0x0200
> +#define CPU_INTERRUPT_TGT_EXT_4 0x1000
> +
> +/*
> + * Several target-specific internal interrupts. These differ from the
> + * preceding target-specific interrupts in that they are intended to
> + * originate from within the cpu itself, typically in response to some
> + * instruction being executed. These, therefore, are not masked while
> + * single-stepping within the debugger.
> + */
> +#define CPU_INTERRUPT_TGT_INT_0 0x0100
> +#define CPU_INTERRUPT_TGT_INT_1 0x0800
> +#define CPU_INTERRUPT_TGT_INT_2 0x2000
> +
> +/* First unused bit: 0x4000. */
> +
> +/* The set of all bits that should be masked when single-stepping. */
> +#define CPU_INTERRUPT_SSTEP_MASK \
> + (CPU_INTERRUPT_HARD \
> + | CPU_INTERRUPT_TGT_EXT_0 \
> + | CPU_INTERRUPT_TGT_EXT_1 \
> + | CPU_INTERRUPT_TGT_EXT_2 \
> + | CPU_INTERRUPT_TGT_EXT_3 \
> + | CPU_INTERRUPT_TGT_EXT_4)
> +
> +#endif /* CPU_INTERRUPT_H */
> diff --git a/include/exec/poison.h b/include/exec/poison.h
> index 35721366d7..8ed04b3108 100644
> --- a/include/exec/poison.h
> +++ b/include/exec/poison.h
> @@ -46,19 +46,6 @@
>
> #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
>
> -#pragma GCC poison CPU_INTERRUPT_HARD
> -#pragma GCC poison CPU_INTERRUPT_EXITTB
> -#pragma GCC poison CPU_INTERRUPT_HALT
> -#pragma GCC poison CPU_INTERRUPT_DEBUG
> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
> -
> #pragma GCC poison CONFIG_ALPHA_DIS
> #pragma GCC poison CONFIG_HPPA_DIS
> #pragma GCC poison CONFIG_I386_DIS
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h
2025-03-07 18:56 ` [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Richard Henderson
2025-03-07 19:11 ` Pierrick Bouvier
@ 2025-03-07 22:03 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 22:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Some of these bits are actually common to all cpus; while the
> reset have common reservations for target-specific usage.
> While generic code cannot know what the target-specific usage is,
> common code can know what to do with the bits, e.g. single-step.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-all.h | 53 +--------------------------
> include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++
> include/exec/poison.h | 13 -------
> 3 files changed, 71 insertions(+), 65 deletions(-)
> create mode 100644 include/exec/cpu-interrupt.h
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
🕺
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 02/16] accel/tcg: Compile watchpoint.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
2025-03-07 18:56 ` [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h Richard Henderson
2025-03-07 18:56 ` [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:12 ` Pierrick Bouvier
2025-03-07 22:02 ` Philippe Mathieu-Daudé
2025-03-07 18:56 ` [PATCH 03/16] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Richard Henderson
` (15 subsequent siblings)
18 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Move tb_check_watchpoint declaration from tb-internal.h, which is
still target-specific, to internal-common.h, which isn't.
Otherwise, all that is required to build watchpoint.c once is
to include the new exec/cpu-interrupt.h instead of exec/exec-all.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/internal-common.h | 2 ++
accel/tcg/tb-internal.h | 2 --
accel/tcg/watchpoint.c | 5 ++---
accel/tcg/meson.build | 2 +-
4 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index 7ef620d963..9b6ab3a8cc 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -72,4 +72,6 @@ void tcg_exec_unrealizefn(CPUState *cpu);
/* current cflags for hashing/comparison */
uint32_t curr_cflags(CPUState *cpu);
+void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
+
#endif
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
index abd423fcf5..62a59a5307 100644
--- a/accel/tcg/tb-internal.h
+++ b/accel/tcg/tb-internal.h
@@ -75,6 +75,4 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
-void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
-
#endif
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index 40112b2b2e..ba8c9859cf 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -19,11 +19,10 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
-#include "qemu/error-report.h"
-#include "exec/exec-all.h"
+#include "exec/breakpoint.h"
+#include "exec/cpu-interrupt.h"
#include "exec/page-protection.h"
#include "exec/translation-block.h"
-#include "tb-internal.h"
#include "system/tcg.h"
#include "system/replay.h"
#include "accel/tcg/cpu-ops.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 69f4808ac4..979ce90eb0 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
- 'watchpoint.c',
'tcg-accel-ops.c',
'tcg-accel-ops-mttcg.c',
'tcg-accel-ops-icount.c',
@@ -30,4 +29,5 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'icount-common.c',
'monitor.c',
+ 'watchpoint.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 02/16] accel/tcg: Compile watchpoint.c once
2025-03-07 18:56 ` [PATCH 02/16] accel/tcg: Compile watchpoint.c once Richard Henderson
@ 2025-03-07 19:12 ` Pierrick Bouvier
2025-03-07 22:02 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Move tb_check_watchpoint declaration from tb-internal.h, which is
> still target-specific, to internal-common.h, which isn't.
> Otherwise, all that is required to build watchpoint.c once is
> to include the new exec/cpu-interrupt.h instead of exec/exec-all.h.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/internal-common.h | 2 ++
> accel/tcg/tb-internal.h | 2 --
> accel/tcg/watchpoint.c | 5 ++---
> accel/tcg/meson.build | 2 +-
> 4 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
> index 7ef620d963..9b6ab3a8cc 100644
> --- a/accel/tcg/internal-common.h
> +++ b/accel/tcg/internal-common.h
> @@ -72,4 +72,6 @@ void tcg_exec_unrealizefn(CPUState *cpu);
> /* current cflags for hashing/comparison */
> uint32_t curr_cflags(CPUState *cpu);
>
> +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
> +
> #endif
> diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
> index abd423fcf5..62a59a5307 100644
> --- a/accel/tcg/tb-internal.h
> +++ b/accel/tcg/tb-internal.h
> @@ -75,6 +75,4 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
>
> bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
>
> -void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
> -
> #endif
> diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
> index 40112b2b2e..ba8c9859cf 100644
> --- a/accel/tcg/watchpoint.c
> +++ b/accel/tcg/watchpoint.c
> @@ -19,11 +19,10 @@
>
> #include "qemu/osdep.h"
> #include "qemu/main-loop.h"
> -#include "qemu/error-report.h"
> -#include "exec/exec-all.h"
> +#include "exec/breakpoint.h"
> +#include "exec/cpu-interrupt.h"
> #include "exec/page-protection.h"
> #include "exec/translation-block.h"
> -#include "tb-internal.h"
> #include "system/tcg.h"
> #include "system/replay.h"
> #include "accel/tcg/cpu-ops.h"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 69f4808ac4..979ce90eb0 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
>
> specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> 'cputlb.c',
> - 'watchpoint.c',
> 'tcg-accel-ops.c',
> 'tcg-accel-ops-mttcg.c',
> 'tcg-accel-ops-icount.c',
> @@ -30,4 +29,5 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> 'icount-common.c',
> 'monitor.c',
> + 'watchpoint.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 02/16] accel/tcg: Compile watchpoint.c once
2025-03-07 18:56 ` [PATCH 02/16] accel/tcg: Compile watchpoint.c once Richard Henderson
2025-03-07 19:12 ` Pierrick Bouvier
@ 2025-03-07 22:02 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 22:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Move tb_check_watchpoint declaration from tb-internal.h, which is
> still target-specific, to internal-common.h, which isn't.
> Otherwise, all that is required to build watchpoint.c once is
> to include the new exec/cpu-interrupt.h instead of exec/exec-all.h.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/internal-common.h | 2 ++
> accel/tcg/tb-internal.h | 2 --
> accel/tcg/watchpoint.c | 5 ++---
> accel/tcg/meson.build | 2 +-
> 4 files changed, 5 insertions(+), 6 deletions(-)
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 03/16] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (2 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 02/16] accel/tcg: Compile watchpoint.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 04/16] exec: Declare tlb_set_page_full() " Richard Henderson
` (14 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20241114011310.3615-14-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cputlb.h | 7 +++++++
include/exec/exec-all.h | 3 ---
include/exec/ram_addr.h | 1 +
system/physmem.c | 1 +
4 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index ef18642a32..6cac7d530f 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr);
#endif /* CONFIG_TCG */
+#ifndef CONFIG_USER_ONLY
+
+void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
+void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
+
+#endif
+
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 8eb0df48f9..f24256fb5e 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -486,9 +486,6 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
#if !defined(CONFIG_USER_ONLY)
-void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
-void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
-
MemoryRegionSection *
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
hwaddr *xlat, hwaddr *plen,
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 94bb3ccbe4..3d8df4edf1 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -23,6 +23,7 @@
#include "cpu.h"
#include "system/xen.h"
#include "system/tcg.h"
+#include "exec/cputlb.h"
#include "exec/ramlist.h"
#include "exec/ramblock.h"
#include "exec/exec-all.h"
diff --git a/system/physmem.c b/system/physmem.c
index 8c1736f84e..a6af555f4b 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -32,6 +32,7 @@
#endif /* CONFIG_TCG */
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "exec/translation-block.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 04/16] exec: Declare tlb_set_page_full() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (3 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 03/16] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 05/16] exec: Declare tlb_set_page_with_attrs() " Richard Henderson
` (13 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241114011310.3615-16-philmd@linaro.org>
---
include/exec/cputlb.h | 23 +++++++++++++++++++++++
include/exec/exec-all.h | 22 ----------------------
target/sparc/mmu_helper.c | 2 +-
3 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 6cac7d530f..733ef012d1 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -21,6 +21,7 @@
#define CPUTLB_H
#include "exec/cpu-common.h"
+#include "exec/vaddr.h"
#ifdef CONFIG_TCG
@@ -39,4 +40,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
#endif
+/**
+ * tlb_set_page_full:
+ * @cpu: CPU context
+ * @mmu_idx: mmu index of the tlb to modify
+ * @addr: virtual address of the entry to add
+ * @full: the details of the tlb entry
+ *
+ * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
+ * @full must be filled, except for xlat_section, and constitute
+ * the complete description of the translated page.
+ *
+ * This is generally called by the target tlb_fill function after
+ * having performed a successful page table walk to find the physical
+ * address and attributes for the translation.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
+ * used by tlb_flush_page.
+ */
+void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
+ CPUTLBEntryFull *full);
+
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f24256fb5e..f43c67366b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -156,28 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
uint16_t idxmap,
unsigned bits);
-/**
- * tlb_set_page_full:
- * @cpu: CPU context
- * @mmu_idx: mmu index of the tlb to modify
- * @addr: virtual address of the entry to add
- * @full: the details of the tlb entry
- *
- * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
- * @full must be filled, except for xlat_section, and constitute
- * the complete description of the translated page.
- *
- * This is generally called by the target tlb_fill function after
- * having performed a successful page table walk to find the physical
- * address and attributes for the translation.
- *
- * At most one entry for a given virtual address is permitted. Only a
- * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
- * used by tlb_flush_page.
- */
-void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
- CPUTLBEntryFull *full);
-
/**
* tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 9ff06026b8..7548d01777 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "qemu/qemu-print.h"
#include "trace.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 05/16] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (4 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 04/16] exec: Declare tlb_set_page_full() " Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 06/16] exec: Declare tlb_set_page() " Richard Henderson
` (12 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241114011310.3615-17-philmd@linaro.org>
---
include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++
include/exec/exec-all.h | 25 -------------------------
target/i386/tcg/system/excp_helper.c | 2 +-
target/microblaze/helper.c | 2 +-
4 files changed, 30 insertions(+), 27 deletions(-)
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 733ef012d1..56dd05a148 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -21,6 +21,8 @@
#define CPUTLB_H
#include "exec/cpu-common.h"
+#include "exec/hwaddr.h"
+#include "exec/memattrs.h"
#include "exec/vaddr.h"
#ifdef CONFIG_TCG
@@ -62,4 +64,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
CPUTLBEntryFull *full);
+/**
+ * tlb_set_page_with_attrs:
+ * @cpu: CPU to add this TLB entry for
+ * @addr: virtual address of page to add entry for
+ * @paddr: physical address of the page
+ * @attrs: memory transaction attributes
+ * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
+ * @mmu_idx: MMU index to insert TLB entry for
+ * @size: size of the page in bytes
+ *
+ * Add an entry to this CPU's TLB (a mapping from virtual address
+ * @addr to physical address @paddr) with the specified memory
+ * transaction attributes. This is generally called by the target CPU
+ * specific code after it has been called through the tlb_fill()
+ * entry point and performed a successful page table walk to find
+ * the physical address and attributes for the virtual address
+ * which provoked the TLB miss.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
+ * used by tlb_flush_page.
+ */
+void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
+ hwaddr paddr, MemTxAttrs attrs,
+ int prot, int mmu_idx, vaddr size);
+
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f43c67366b..62d6300752 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -156,31 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
uint16_t idxmap,
unsigned bits);
-/**
- * tlb_set_page_with_attrs:
- * @cpu: CPU to add this TLB entry for
- * @addr: virtual address of page to add entry for
- * @paddr: physical address of the page
- * @attrs: memory transaction attributes
- * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
- * @mmu_idx: MMU index to insert TLB entry for
- * @size: size of the page in bytes
- *
- * Add an entry to this CPU's TLB (a mapping from virtual address
- * @addr to physical address @paddr) with the specified memory
- * transaction attributes. This is generally called by the target CPU
- * specific code after it has been called through the tlb_fill()
- * entry point and performed a successful page table walk to find
- * the physical address and attributes for the virtual address
- * which provoked the TLB miss.
- *
- * At most one entry for a given virtual address is permitted. Only a
- * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
- * used by tlb_flush_page.
- */
-void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
- hwaddr paddr, MemTxAttrs attrs,
- int prot, int mmu_idx, vaddr size);
/* tlb_set_page:
*
* This function is equivalent to calling tlb_set_page_with_attrs()
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index 864e3140e3..6876329de2 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/cpu_ldst.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "tcg/helper-tcg.h"
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5d3259ce31..27fc929bee 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "qemu/host-utils.h"
#include "exec/log.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 06/16] exec: Declare tlb_set_page() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (5 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 05/16] exec: Declare tlb_set_page_with_attrs() " Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 07/16] exec: Declare tlb_hit*() " Richard Henderson
` (11 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241114011310.3615-18-philmd@linaro.org>
---
include/exec/cputlb.h | 11 +++++++++++
include/exec/exec-all.h | 9 ---------
target/alpha/helper.c | 2 +-
target/avr/helper.c | 2 +-
target/loongarch/tcg/tlb_helper.c | 1 +
target/m68k/helper.c | 1 +
target/mips/tcg/system/tlb_helper.c | 1 +
target/openrisc/mmu.c | 2 +-
target/ppc/mmu_helper.c | 1 +
target/riscv/cpu_helper.c | 1 +
target/rx/cpu.c | 2 +-
target/s390x/tcg/excp_helper.c | 1 +
target/sh4/helper.c | 1 +
target/tricore/helper.c | 2 +-
target/xtensa/helper.c | 2 +-
15 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 56dd05a148..cdfaf17403 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -90,4 +90,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
hwaddr paddr, MemTxAttrs attrs,
int prot, int mmu_idx, vaddr size);
+/**
+ * tlb_set_page:
+ *
+ * This function is equivalent to calling tlb_set_page_with_attrs()
+ * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
+ * as a convenience for CPUs which don't use memory transaction attributes.
+ */
+void tlb_set_page(CPUState *cpu, vaddr addr,
+ hwaddr paddr, int prot,
+ int mmu_idx, vaddr size);
+
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 62d6300752..a3aa8448d0 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -156,15 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
uint16_t idxmap,
unsigned bits);
-/* tlb_set_page:
- *
- * This function is equivalent to calling tlb_set_page_with_attrs()
- * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
- * as a convenience for CPUs which don't use memory transaction attributes.
- */
-void tlb_set_page(CPUState *cpu, vaddr addr,
- hwaddr paddr, int prot,
- int mmu_idx, vaddr size);
#else
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
{
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 2f1000c99f..57cefcba14 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "fpu/softfloat-types.h"
#include "exec/helper-proto.h"
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 9ea6870e44..3412312ad5 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -23,7 +23,7 @@
#include "qemu/error-report.h"
#include "cpu.h"
#include "accel/tcg/cpu-ops.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index a323606e5a..f6b63c7224 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -12,6 +12,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/helper-proto.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index beefeb7069..0bf574830f 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/gdbstub.h"
diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c
index e98bb95951..ca4d6b27bc 100644
--- a/target/mips/tcg/system/tlb_helper.c
+++ b/target/mips/tcg/system/tlb_helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "internal.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index c632d5230b..47ac783c52 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "gdbstub/helpers.h"
#include "qemu/host-utils.h"
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index a802bc9c62..ad9ba8294c 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -24,6 +24,7 @@
#include "kvm_ppc.h"
#include "mmu-hash64.h"
#include "mmu-hash32.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/log.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 34092f372d..6c4391d96b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -23,6 +23,7 @@
#include "cpu.h"
#include "internals.h"
#include "pmu.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "instmap.h"
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 1c40c8977e..f01e069a90 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -21,7 +21,7 @@
#include "qapi/error.h"
#include "cpu.h"
#include "migration/vmstate.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/translation-block.h"
#include "hw/loader.h"
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index 4c0b692c9e..f969850f87 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "s390x-internal.h"
#include "tcg_s390x.h"
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index b8774e046e..7567e6c8b6 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/log.h"
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 9898752eb0..a64412e6bd 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -19,7 +19,7 @@
#include "qemu/log.h"
#include "hw/registerfields.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "fpu/softfloat-helpers.h"
#include "qemu/qemu-print.h"
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f64699b116..4824b97e37 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -28,7 +28,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "gdbstub/helpers.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 07/16] exec: Declare tlb_hit*() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (6 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 06/16] exec: Declare tlb_set_page() " Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 08/16] exec: Declare tlb_flush*() " Richard Henderson
` (10 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241114011310.3615-20-philmd@linaro.org>
---
include/exec/cpu-all.h | 23 -----------------------
accel/tcg/cputlb.c | 23 +++++++++++++++++++++++
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 9e6724097c..8cd6c00cf8 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -179,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
/* The two sets of flags must not overlap. */
QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
-/**
- * tlb_hit_page: return true if page aligned @addr is a hit against the
- * TLB entry @tlb_addr
- *
- * @addr: virtual address to test (must be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
-{
- return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-}
-
-/**
- * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
- *
- * @addr: virtual address to test (need not be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
-{
- return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
-}
-
#endif /* !CONFIG_USER_ONLY */
/* Validate correct placement of CPUArchState. */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index c8761683a0..fb22048876 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1201,6 +1201,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr,
prot, mmu_idx, size);
}
+/**
+ * tlb_hit_page: return true if page aligned @addr is a hit against the
+ * TLB entry @tlb_addr
+ *
+ * @addr: virtual address to test (must be page aligned)
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
+ */
+static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
+{
+ return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
+}
+
+/**
+ * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
+ *
+ * @addr: virtual address to test (need not be page aligned)
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
+ */
+static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
+{
+ return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
+}
+
/*
* Note: tlb_fill_align() can trigger a resize of the TLB.
* This means that all of the caller's prior references to the TLB table
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 08/16] exec: Declare tlb_flush*() in 'exec/cputlb.h'
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (7 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 07/16] exec: Declare tlb_hit*() " Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 18:56 ` [PATCH 09/16] system: Build watchpoint.c once Richard Henderson
` (9 subsequent siblings)
18 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd, Pierrick Bouvier
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20241114011310.3615-19-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cputlb.h | 200 +++++++++++++++++++++++++--
include/exec/exec-all.h | 184 ------------------------
accel/tcg/tcg-accel-ops.c | 2 +-
cpu-target.c | 1 +
hw/intc/armv7m_nvic.c | 2 +-
hw/ppc/spapr_nested.c | 1 +
hw/sh4/sh7750.c | 1 +
system/watchpoint.c | 3 +-
target/alpha/sys_helper.c | 2 +-
target/arm/helper.c | 1 +
target/arm/tcg/tlb-insns.c | 2 +-
target/hppa/mem_helper.c | 1 +
target/i386/helper.c | 2 +-
target/i386/machine.c | 2 +-
target/i386/tcg/fpu_helper.c | 2 +-
target/i386/tcg/misc_helper.c | 2 +-
target/i386/tcg/system/misc_helper.c | 2 +-
target/i386/tcg/system/svm_helper.c | 2 +-
target/loongarch/tcg/csr_helper.c | 2 +-
target/microblaze/mmu.c | 2 +-
target/mips/system/cp0.c | 2 +-
target/mips/tcg/system/cp0_helper.c | 2 +-
target/openrisc/sys_helper.c | 1 +
target/ppc/helper_regs.c | 2 +-
target/ppc/misc_helper.c | 1 +
target/riscv/csr.c | 1 +
target/riscv/op_helper.c | 1 +
target/riscv/pmp.c | 2 +-
target/s390x/gdbstub.c | 2 +-
target/s390x/sigp.c | 1 +
target/s390x/tcg/mem_helper.c | 1 +
target/s390x/tcg/misc_helper.c | 1 +
target/sparc/ldst_helper.c | 1 +
target/xtensa/mmu_helper.c | 1 +
34 files changed, 224 insertions(+), 211 deletions(-)
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index cdfaf17403..8125f6809c 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -25,21 +25,14 @@
#include "exec/memattrs.h"
#include "exec/vaddr.h"
-#ifdef CONFIG_TCG
-
-#if !defined(CONFIG_USER_ONLY)
-/* cputlb.c */
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
void tlb_protect_code(ram_addr_t ram_addr);
void tlb_unprotect_code(ram_addr_t ram_addr);
#endif
-#endif /* CONFIG_TCG */
-
#ifndef CONFIG_USER_ONLY
-
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
-
#endif
/**
@@ -101,4 +94,193 @@ void tlb_set_page(CPUState *cpu, vaddr addr,
hwaddr paddr, int prot,
int mmu_idx, vaddr size);
-#endif
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+/**
+ * tlb_flush_page:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of the specified CPU, for all
+ * MMU indexes.
+ */
+void tlb_flush_page(CPUState *cpu, vaddr addr);
+
+/**
+ * tlb_flush_page_all_cpus_synced:
+ * @cpu: src CPU of the flush
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of all CPUs, for all
+ * MMU indexes.
+ *
+ * When this function returns, no CPUs will subsequently perform
+ * translations using the flushed TLBs.
+ */
+void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
+
+/**
+ * tlb_flush:
+ * @cpu: CPU whose TLB should be flushed
+ *
+ * Flush the entire TLB for the specified CPU. Most CPU architectures
+ * allow the implementation to drop entries from the TLB at any time
+ * so this is generally safe. If more selective flushing is required
+ * use one of the other functions for efficiency.
+ */
+void tlb_flush(CPUState *cpu);
+
+/**
+ * tlb_flush_all_cpus_synced:
+ * @cpu: src CPU of the flush
+ *
+ * Flush the entire TLB for all CPUs, for all MMU indexes.
+ *
+ * When this function returns, no CPUs will subsequently perform
+ * translations using the flushed TLBs.
+ */
+void tlb_flush_all_cpus_synced(CPUState *src_cpu);
+
+/**
+ * tlb_flush_page_by_mmuidx:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush one page from the TLB of the specified CPU, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
+ uint16_t idxmap);
+
+/**
+ * tlb_flush_page_by_mmuidx_all_cpus_synced:
+ * @cpu: Originating CPU of the flush
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush one page from the TLB of all CPUs, for the specified
+ * MMU indexes.
+ *
+ * When this function returns, no CPUs will subsequently perform
+ * translations using the flushed TLBs.
+ */
+void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
+ uint16_t idxmap);
+
+/**
+ * tlb_flush_by_mmuidx:
+ * @cpu: CPU whose TLB should be flushed
+ * @wait: If true ensure synchronisation by exiting the cpu_loop
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush all entries from the TLB of the specified CPU, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
+
+/**
+ * tlb_flush_by_mmuidx_all_cpus_synced:
+ * @cpu: Originating CPU of the flush
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush all entries from the TLB of all CPUs, for the specified
+ * MMU indexes.
+ *
+ * When this function returns, no CPUs will subsequently perform
+ * translations using the flushed TLBs.
+ */
+void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
+
+/**
+ * tlb_flush_page_bits_by_mmuidx
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of mmu indexes to flush
+ * @bits: number of significant bits in address
+ *
+ * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
+ */
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
+ uint16_t idxmap, unsigned bits);
+
+/* Similarly, with broadcast and syncing. */
+void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
+ uint16_t idxmap,
+ unsigned bits);
+
+/**
+ * tlb_flush_range_by_mmuidx
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of the start of the range to be flushed
+ * @len: length of range to be flushed
+ * @idxmap: bitmap of mmu indexes to flush
+ * @bits: number of significant bits in address
+ *
+ * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
+ * comparing only the low @bits worth of each virtual page.
+ */
+void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
+ vaddr len, uint16_t idxmap,
+ unsigned bits);
+
+/* Similarly, with broadcast and syncing. */
+void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ vaddr len,
+ uint16_t idxmap,
+ unsigned bits);
+#else
+static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
+{
+}
+static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
+{
+}
+static inline void tlb_flush(CPUState *cpu)
+{
+}
+static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
+{
+}
+static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
+ vaddr addr, uint16_t idxmap)
+{
+}
+
+static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
+{
+}
+static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap)
+{
+}
+static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ uint16_t idxmap)
+{
+}
+static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void
+tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
+ uint16_t idxmap, unsigned bits)
+{
+}
+static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
+ vaddr len, uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ vaddr len,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+#endif /* CPUTLB_H */
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a3aa8448d0..a758b7a843 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -27,190 +27,6 @@
#include "exec/mmu-access-type.h"
#include "exec/translation-block.h"
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
-/* cputlb.c */
-/**
- * tlb_flush_page:
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- *
- * Flush one page from the TLB of the specified CPU, for all
- * MMU indexes.
- */
-void tlb_flush_page(CPUState *cpu, vaddr addr);
-/**
- * tlb_flush_page_all_cpus_synced:
- * @cpu: src CPU of the flush
- * @addr: virtual address of page to be flushed
- *
- * Flush one page from the TLB of all CPUs, for all
- * MMU indexes.
- *
- * When this function returns, no CPUs will subsequently perform
- * translations using the flushed TLBs.
- */
-void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
-/**
- * tlb_flush:
- * @cpu: CPU whose TLB should be flushed
- *
- * Flush the entire TLB for the specified CPU. Most CPU architectures
- * allow the implementation to drop entries from the TLB at any time
- * so this is generally safe. If more selective flushing is required
- * use one of the other functions for efficiency.
- */
-void tlb_flush(CPUState *cpu);
-/**
- * tlb_flush_all_cpus_synced:
- * @cpu: src CPU of the flush
- *
- * Flush the entire TLB for all CPUs, for all MMU indexes.
- *
- * When this function returns, no CPUs will subsequently perform
- * translations using the flushed TLBs.
- */
-void tlb_flush_all_cpus_synced(CPUState *src_cpu);
-/**
- * tlb_flush_page_by_mmuidx:
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush one page from the TLB of the specified CPU, for the specified
- * MMU indexes.
- */
-void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
- uint16_t idxmap);
-/**
- * tlb_flush_page_by_mmuidx_all_cpus_synced:
- * @cpu: Originating CPU of the flush
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush one page from the TLB of all CPUs, for the specified
- * MMU indexes.
- *
- * When this function returns, no CPUs will subsequently perform
- * translations using the flushed TLBs.
- */
-void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
- uint16_t idxmap);
-/**
- * tlb_flush_by_mmuidx:
- * @cpu: CPU whose TLB should be flushed
- * @wait: If true ensure synchronisation by exiting the cpu_loop
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush all entries from the TLB of the specified CPU, for the specified
- * MMU indexes.
- */
-void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
-/**
- * tlb_flush_by_mmuidx_all_cpus_synced:
- * @cpu: Originating CPU of the flush
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush all entries from the TLB of all CPUs, for the specified
- * MMU indexes.
- *
- * When this function returns, no CPUs will subsequently perform
- * translations using the flushed TLBs.
- */
-void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
-
-/**
- * tlb_flush_page_bits_by_mmuidx
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of mmu indexes to flush
- * @bits: number of significant bits in address
- *
- * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
- */
-void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
- uint16_t idxmap, unsigned bits);
-
-/* Similarly, with broadcast and syncing. */
-void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
- (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
-
-/**
- * tlb_flush_range_by_mmuidx
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of the start of the range to be flushed
- * @len: length of range to be flushed
- * @idxmap: bitmap of mmu indexes to flush
- * @bits: number of significant bits in address
- *
- * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
- * comparing only the low @bits worth of each virtual page.
- */
-void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
- vaddr len, uint16_t idxmap,
- unsigned bits);
-
-/* Similarly, with broadcast and syncing. */
-void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- vaddr len,
- uint16_t idxmap,
- unsigned bits);
-
-#else
-static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
-{
-}
-static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
-{
-}
-static inline void tlb_flush(CPUState *cpu)
-{
-}
-static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
-{
-}
-static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
- vaddr addr, uint16_t idxmap)
-{
-}
-
-static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
-{
-}
-static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap)
-{
-}
-static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
- uint16_t idxmap)
-{
-}
-static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void
-tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
- uint16_t idxmap, unsigned bits)
-{
-}
-static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
- vaddr len, uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- vaddr len,
- uint16_t idxmap,
- unsigned bits)
-{
-}
-#endif
-
#if defined(CONFIG_TCG)
/**
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 132c5d1461..53e580d128 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -33,7 +33,7 @@
#include "qemu/main-loop.h"
#include "qemu/guest-random.h"
#include "qemu/timer.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/hwaddr.h"
#include "exec/tb-flush.h"
#include "exec/translation-block.h"
diff --git a/cpu-target.c b/cpu-target.c
index 5aa6c4b0c6..b6e66d5ac0 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -31,6 +31,7 @@
#include "exec/tswap.h"
#include "exec/replay-core.h"
#include "exec/cpu-common.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
#include "exec/log.h"
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 5fd0760982..7212c87c68 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -22,7 +22,7 @@
#include "system/runstate.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-features.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/memop.h"
#include "qemu/log.h"
#include "qemu/module.h"
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 7def8eb73b..23958c6383 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "helper_regs.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/spapr.h"
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 8892eaddcb..6faf0e3ca8 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -36,6 +36,7 @@
#include "hw/sh4/sh_intc.h"
#include "hw/timer/tmu012.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "trace.h"
typedef struct SH7750State {
diff --git a/system/watchpoint.c b/system/watchpoint.c
index 2aa2a9ea63..08dbd8483d 100644
--- a/system/watchpoint.c
+++ b/system/watchpoint.c
@@ -19,7 +19,8 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
+#include "exec/target_page.h"
#include "hw/core/cpu.h"
/* Add a watchpoint. */
diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c
index 54ee93f34c..51e3254428 100644
--- a/target/alpha/sys_helper.c
+++ b/target/alpha/sys_helper.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/tb-flush.h"
#include "exec/helper-proto.h"
#include "system/runstate.h"
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 71dead7241..e786c8df5f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -18,6 +18,7 @@
#include "qemu/timer.h"
#include "qemu/bitops.h"
#include "qemu/qemu-print.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "hw/irq.h"
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index fadc61a76e..630a481f0f 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -7,7 +7,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "cpu.h"
#include "internals.h"
#include "cpu-features.h"
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 304f0b61e2..fb1d93ef1f 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "hw/core/cpu.h"
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 3bc15fba6e..c07b1b16ea 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "qapi/qapi-events-run-state.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/translation-block.h"
#include "system/runstate.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/i386/machine.c b/target/i386/machine.c
index d9d4f25d1a..70f632a36f 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1,6 +1,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "hw/isa/isa.h"
#include "migration/cpu.h"
#include "kvm/hyperv.h"
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 4858ae9a5f..c1184ca219 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -21,7 +21,7 @@
#include <math.h>
#include "cpu.h"
#include "tcg-cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index ed4cda8001..2b5f092a23 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -21,7 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "helper-tcg.h"
/*
diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c
index c9c4d42f84..ce18c75b9f 100644
--- a/target/i386/tcg/system/misc_helper.c
+++ b/target/i386/tcg/system/misc_helper.c
@@ -23,7 +23,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "tcg/helper-tcg.h"
#include "hw/i386/apic.h"
diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c
index 5f95b5227b..f9982b72d1 100644
--- a/target/i386/tcg/system/svm_helper.c
+++ b/target/i386/tcg/system/svm_helper.c
@@ -21,7 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "tcg/helper-tcg.h"
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 6c95be9910..84f7ff25f6 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -12,7 +12,7 @@
#include "internals.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "hw/irq.h"
#include "cpu-csr.h"
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 2423ac6172..f8587d5ac4 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
static unsigned int tlb_decode_size(unsigned int f)
diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c
index bae37f515b..ff7d3db00c 100644
--- a/target/mips/system/cp0.c
+++ b/target/mips/system/cp0.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
/* Called for updates to CP0_Status. */
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c
index 79a5c833ce..01a07a169f 100644
--- a/target/mips/tcg/system/cp0_helper.c
+++ b/target/mips/tcg/system/cp0_helper.c
@@ -27,7 +27,7 @@
#include "internal.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
/* SMP helpers. */
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 77567afba4..21bc137ccc 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/helper-proto.h"
#include "exception.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 3ad4273c16..f211bc9830 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/main-loop.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "system/kvm.h"
#include "system/tcg.h"
#include "helper_regs.h"
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index f0ca80153b..e379da6010 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0ebcca4597..49566d3c08 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -25,6 +25,7 @@
#include "pmu.h"
#include "time_helper.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/tb-flush.h"
#include "system/cpu-timers.h"
#include "qemu/guest-random.h"
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f156bfab12..0d4220ba93 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "trace.h"
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 85ab270dad..b0841d44f4 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -24,7 +24,7 @@
#include "qapi/error.h"
#include "cpu.h"
#include "trace.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index 6879430adc..6bca376f2b 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "s390x-internal.h"
-#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/gdbstub.h"
#include "gdbstub/helpers.h"
#include "qemu/bitops.h"
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index cf53b23291..6a4d9c5081 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -15,6 +15,7 @@
#include "system/hw_accel.h"
#include "system/runstate.h"
#include "exec/address-spaces.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "system/tcg.h"
#include "trace.h"
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index ea9fa64d6b..8187b917ba 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -26,6 +26,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "accel/tcg/cpu-ops.h"
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index 0245451472..31266aeda4 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -27,6 +27,7 @@
#include "exec/helper-proto.h"
#include "qemu/timer.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "qapi/error.h"
#include "tcg_s390x.h"
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 4c54e45655..b559afc9a9 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -24,6 +24,7 @@
#include "tcg/tcg.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#ifdef CONFIG_USER_ONLY
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 29b84d5dbf..63be741a42 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -32,6 +32,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
+#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 09/16] system: Build watchpoint.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (8 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 08/16] exec: Declare tlb_flush*() " Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:12 ` Pierrick Bouvier
2025-03-07 21:57 ` Philippe Mathieu-Daudé
2025-03-07 18:56 ` [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once Richard Henderson
` (8 subsequent siblings)
18 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Now that watchpoint.c uses cputlb.h instead of exec-all.h,
it can be built once.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
system/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index 4952f4b2c7..c83d80fa24 100644
--- a/system/meson.build
+++ b/system/meson.build
@@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files(
'ioport.c',
'memory.c',
'physmem.c',
- 'watchpoint.c',
)])
system_ss.add(files(
@@ -24,6 +23,7 @@ system_ss.add(files(
'runstate.c',
'tpm-hmp-cmds.c',
'vl.c',
+ 'watchpoint.c',
), sdl, libpmem, libdaxctl)
if have_tpm
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 09/16] system: Build watchpoint.c once
2025-03-07 18:56 ` [PATCH 09/16] system: Build watchpoint.c once Richard Henderson
@ 2025-03-07 19:12 ` Pierrick Bouvier
2025-03-07 21:57 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Now that watchpoint.c uses cputlb.h instead of exec-all.h,
> it can be built once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> system/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/system/meson.build b/system/meson.build
> index 4952f4b2c7..c83d80fa24 100644
> --- a/system/meson.build
> +++ b/system/meson.build
> @@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files(
> 'ioport.c',
> 'memory.c',
> 'physmem.c',
> - 'watchpoint.c',
> )])
>
> system_ss.add(files(
> @@ -24,6 +23,7 @@ system_ss.add(files(
> 'runstate.c',
> 'tpm-hmp-cmds.c',
> 'vl.c',
> + 'watchpoint.c',
> ), sdl, libpmem, libdaxctl)
>
> if have_tpm
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 09/16] system: Build watchpoint.c once
2025-03-07 18:56 ` [PATCH 09/16] system: Build watchpoint.c once Richard Henderson
2025-03-07 19:12 ` Pierrick Bouvier
@ 2025-03-07 21:57 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 21:57 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Now that watchpoint.c uses cputlb.h instead of exec-all.h,
> it can be built once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> system/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
❤️🩹
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (9 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 09/16] system: Build watchpoint.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once Richard Henderson
` (7 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h,
it can be built once.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 979ce90eb0..70ada21f42 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
- 'tcg-accel-ops.c',
'tcg-accel-ops-mttcg.c',
'tcg-accel-ops-icount.c',
'tcg-accel-ops-rr.c',
@@ -29,5 +28,6 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'icount-common.c',
'monitor.c',
+ 'tcg-accel-ops.c',
'watchpoint.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once
2025-03-07 18:56 ` [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h,
> it can be built once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 979ce90eb0..70ada21f42 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
>
> specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> 'cputlb.c',
> - 'tcg-accel-ops.c',
> 'tcg-accel-ops-mttcg.c',
> 'tcg-accel-ops-icount.c',
> 'tcg-accel-ops-rr.c',
> @@ -29,5 +28,6 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> 'icount-common.c',
> 'monitor.c',
> + 'tcg-accel-ops.c',
> 'watchpoint.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (10 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once Richard Henderson
` (6 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
All that is required is to avoid including exec-all.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-accel-ops-icount.c | 2 +-
accel/tcg/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
index d6b472a0b0..27cf1044c7 100644
--- a/accel/tcg/tcg-accel-ops-icount.c
+++ b/accel/tcg/tcg-accel-ops-icount.c
@@ -28,7 +28,7 @@
#include "system/cpu-timers.h"
#include "qemu/main-loop.h"
#include "qemu/guest-random.h"
-#include "exec/exec-all.h"
+#include "hw/core/cpu.h"
#include "tcg-accel-ops.h"
#include "tcg-accel-ops-icount.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 70ada21f42..891b724eb6 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
'tcg-accel-ops-mttcg.c',
- 'tcg-accel-ops-icount.c',
'tcg-accel-ops-rr.c',
))
@@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'icount-common.c',
'monitor.c',
'tcg-accel-ops.c',
+ 'tcg-accel-ops-icount.c',
'watchpoint.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once
2025-03-07 18:56 ` [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> All that is required is to avoid including exec-all.h.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-accel-ops-icount.c | 2 +-
> accel/tcg/meson.build | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
> index d6b472a0b0..27cf1044c7 100644
> --- a/accel/tcg/tcg-accel-ops-icount.c
> +++ b/accel/tcg/tcg-accel-ops-icount.c
> @@ -28,7 +28,7 @@
> #include "system/cpu-timers.h"
> #include "qemu/main-loop.h"
> #include "qemu/guest-random.h"
> -#include "exec/exec-all.h"
> +#include "hw/core/cpu.h"
>
> #include "tcg-accel-ops.h"
> #include "tcg-accel-ops-icount.h"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 70ada21f42..891b724eb6 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
> specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> 'cputlb.c',
> 'tcg-accel-ops-mttcg.c',
> - 'tcg-accel-ops-icount.c',
> 'tcg-accel-ops-rr.c',
> ))
>
> @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> 'icount-common.c',
> 'monitor.c',
> 'tcg-accel-ops.c',
> + 'tcg-accel-ops-icount.c',
> 'watchpoint.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (11 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once Richard Henderson
` (5 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
All that is required is to use cpu-common.h instead of exec-all.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-accel-ops-rr.c | 2 +-
accel/tcg/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
index 028b385af9..f62cf24e1d 100644
--- a/accel/tcg/tcg-accel-ops-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -31,7 +31,7 @@
#include "qemu/main-loop.h"
#include "qemu/notify.h"
#include "qemu/guest-random.h"
-#include "exec/exec-all.h"
+#include "exec/cpu-common.h"
#include "tcg/startup.h"
#include "tcg-accel-ops.h"
#include "tcg-accel-ops-rr.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 891b724eb6..87c1394b62 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
'tcg-accel-ops-mttcg.c',
- 'tcg-accel-ops-rr.c',
))
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
@@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'monitor.c',
'tcg-accel-ops.c',
'tcg-accel-ops-icount.c',
+ 'tcg-accel-ops-rr.c',
'watchpoint.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once
2025-03-07 18:56 ` [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> All that is required is to use cpu-common.h instead of exec-all.h.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-accel-ops-rr.c | 2 +-
> accel/tcg/meson.build | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
> index 028b385af9..f62cf24e1d 100644
> --- a/accel/tcg/tcg-accel-ops-rr.c
> +++ b/accel/tcg/tcg-accel-ops-rr.c
> @@ -31,7 +31,7 @@
> #include "qemu/main-loop.h"
> #include "qemu/notify.h"
> #include "qemu/guest-random.h"
> -#include "exec/exec-all.h"
> +#include "exec/cpu-common.h"
> #include "tcg/startup.h"
> #include "tcg-accel-ops.h"
> #include "tcg-accel-ops-rr.h"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 891b724eb6..87c1394b62 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
> specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> 'cputlb.c',
> 'tcg-accel-ops-mttcg.c',
> - 'tcg-accel-ops-rr.c',
> ))
>
> system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> 'monitor.c',
> 'tcg-accel-ops.c',
> 'tcg-accel-ops-icount.c',
> + 'tcg-accel-ops-rr.c',
> 'watchpoint.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (12 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 14/16] include/exec: Split out helper-getpc.h Richard Henderson
` (4 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
All that is required is to avoid including exec-all.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-accel-ops-mttcg.c | 1 -
accel/tcg/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
index ba7cf6819d..bdcc385ae9 100644
--- a/accel/tcg/tcg-accel-ops-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -30,7 +30,6 @@
#include "qemu/main-loop.h"
#include "qemu/notify.h"
#include "qemu/guest-random.h"
-#include "exec/exec-all.h"
#include "hw/boards.h"
#include "tcg/startup.h"
#include "tcg-accel-ops.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 87c1394b62..81fb25da5c 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
- 'tcg-accel-ops-mttcg.c',
))
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
@@ -28,6 +27,7 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'monitor.c',
'tcg-accel-ops.c',
'tcg-accel-ops-icount.c',
+ 'tcg-accel-ops-mttcg.c',
'tcg-accel-ops-rr.c',
'watchpoint.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once
2025-03-07 18:56 ` [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> All that is required is to avoid including exec-all.h.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-accel-ops-mttcg.c | 1 -
> accel/tcg/meson.build | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
> index ba7cf6819d..bdcc385ae9 100644
> --- a/accel/tcg/tcg-accel-ops-mttcg.c
> +++ b/accel/tcg/tcg-accel-ops-mttcg.c
> @@ -30,7 +30,6 @@
> #include "qemu/main-loop.h"
> #include "qemu/notify.h"
> #include "qemu/guest-random.h"
> -#include "exec/exec-all.h"
> #include "hw/boards.h"
> #include "tcg/startup.h"
> #include "tcg-accel-ops.h"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 87c1394b62..81fb25da5c 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
>
> specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
> 'cputlb.c',
> - 'tcg-accel-ops-mttcg.c',
> ))
>
> system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> @@ -28,6 +27,7 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
> 'monitor.c',
> 'tcg-accel-ops.c',
> 'tcg-accel-ops-icount.c',
> + 'tcg-accel-ops-mttcg.c',
> 'tcg-accel-ops-rr.c',
> 'watchpoint.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 14/16] include/exec: Split out helper-getpc.h
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (13 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 22:00 ` Philippe Mathieu-Daudé
2025-03-07 18:56 ` [PATCH 15/16] accel/tcg: Build tcg-runtime.c once Richard Henderson
` (3 subsequent siblings)
18 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Split out GETPC and GETPC_ADJ to a target-independent header.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 19 +------------------
include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+), 18 deletions(-)
create mode 100644 include/exec/helper-getpc.h
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a758b7a843..22a99ca502 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -26,6 +26,7 @@
#endif
#include "exec/mmu-access-type.h"
#include "exec/translation-block.h"
+#include "exec/helper-getpc.h"
#if defined(CONFIG_TCG)
@@ -177,24 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
-/* GETPC is the true target of the return instruction that we'll execute. */
-#if defined(CONFIG_TCG_INTERPRETER)
-extern __thread uintptr_t tci_tb_ptr;
-# define GETPC() tci_tb_ptr
-#else
-# define GETPC() \
- ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
-#endif
-
-/* The true return address will often point to a host insn that is part of
- the next translated guest insn. Adjust the address backward to point to
- the middle of the call insn. Subtracting one would do the job except for
- several compressed mode architectures (arm, mips) which set the low bit
- to indicate the compressed mode; subtracting two works around that. It
- is also the case that there are no host isas that contain a call insn
- smaller than 4 bytes, so we don't worry about special-casing this. */
-#define GETPC_ADJ 2
-
#if !defined(CONFIG_USER_ONLY)
/**
diff --git a/include/exec/helper-getpc.h b/include/exec/helper-getpc.h
new file mode 100644
index 0000000000..1c8bd72c11
--- /dev/null
+++ b/include/exec/helper-getpc.h
@@ -0,0 +1,31 @@
+/*
+ * Get host pc for helper unwinding.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef HELPER_GETPC_H
+#define HELPER_GETPC_H
+
+/* GETPC is the true target of the return instruction that we'll execute. */
+#if defined(CONFIG_TCG_INTERPRETER)
+extern __thread uintptr_t tci_tb_ptr;
+# define GETPC() tci_tb_ptr
+#else
+# define GETPC() \
+ ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
+#endif
+
+/*
+ * The true return address will often point to a host insn that is part of
+ * the next translated guest insn. Adjust the address backward to point to
+ * the middle of the call insn. Subtracting one would do the job except for
+ * several compressed mode architectures (arm, mips) which set the low bit
+ * to indicate the compressed mode; subtracting two works around that. It
+ * is also the case that there are no host isas that contain a call insn
+ * smaller than 4 bytes, so we don't worry about special-casing this.
+ */
+#define GETPC_ADJ 2
+
+#endif /* HELPER_GETPC_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 14/16] include/exec: Split out helper-getpc.h
2025-03-07 18:56 ` [PATCH 14/16] include/exec: Split out helper-getpc.h Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 22:00 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Split out GETPC and GETPC_ADJ to a target-independent header.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 19 +------------------
> include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+), 18 deletions(-)
> create mode 100644 include/exec/helper-getpc.h
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index a758b7a843..22a99ca502 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -26,6 +26,7 @@
> #endif
> #include "exec/mmu-access-type.h"
> #include "exec/translation-block.h"
> +#include "exec/helper-getpc.h"
>
> #if defined(CONFIG_TCG)
>
> @@ -177,24 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
> void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
> void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
>
> -/* GETPC is the true target of the return instruction that we'll execute. */
> -#if defined(CONFIG_TCG_INTERPRETER)
> -extern __thread uintptr_t tci_tb_ptr;
> -# define GETPC() tci_tb_ptr
> -#else
> -# define GETPC() \
> - ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
> -#endif
> -
> -/* The true return address will often point to a host insn that is part of
> - the next translated guest insn. Adjust the address backward to point to
> - the middle of the call insn. Subtracting one would do the job except for
> - several compressed mode architectures (arm, mips) which set the low bit
> - to indicate the compressed mode; subtracting two works around that. It
> - is also the case that there are no host isas that contain a call insn
> - smaller than 4 bytes, so we don't worry about special-casing this. */
> -#define GETPC_ADJ 2
> -
> #if !defined(CONFIG_USER_ONLY)
>
> /**
> diff --git a/include/exec/helper-getpc.h b/include/exec/helper-getpc.h
> new file mode 100644
> index 0000000000..1c8bd72c11
> --- /dev/null
> +++ b/include/exec/helper-getpc.h
> @@ -0,0 +1,31 @@
> +/*
> + * Get host pc for helper unwinding.
> + *
> + * Copyright (c) 2003 Fabrice Bellard
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#ifndef HELPER_GETPC_H
> +#define HELPER_GETPC_H
> +
> +/* GETPC is the true target of the return instruction that we'll execute. */
> +#if defined(CONFIG_TCG_INTERPRETER)
> +extern __thread uintptr_t tci_tb_ptr;
> +# define GETPC() tci_tb_ptr
> +#else
> +# define GETPC() \
> + ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
> +#endif
> +
> +/*
> + * The true return address will often point to a host insn that is part of
> + * the next translated guest insn. Adjust the address backward to point to
> + * the middle of the call insn. Subtracting one would do the job except for
> + * several compressed mode architectures (arm, mips) which set the low bit
> + * to indicate the compressed mode; subtracting two works around that. It
> + * is also the case that there are no host isas that contain a call insn
> + * smaller than 4 bytes, so we don't worry about special-casing this.
> + */
> +#define GETPC_ADJ 2
> +
> +#endif /* HELPER_GETPC_H */
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 14/16] include/exec: Split out helper-getpc.h
2025-03-07 18:56 ` [PATCH 14/16] include/exec: Split out helper-getpc.h Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
@ 2025-03-07 22:00 ` Philippe Mathieu-Daudé
2025-03-07 22:23 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 22:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Split out GETPC and GETPC_ADJ to a target-independent header.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 19 +------------------
> include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+), 18 deletions(-)
> create mode 100644 include/exec/helper-getpc.h
Preferably include/accel/tcg/getpc.h or similar, otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 14/16] include/exec: Split out helper-getpc.h
2025-03-07 22:00 ` Philippe Mathieu-Daudé
@ 2025-03-07 22:23 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 22:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 23:00, Philippe Mathieu-Daudé wrote:
> On 7/3/25 19:56, Richard Henderson wrote:
>> Split out GETPC and GETPC_ADJ to a target-independent header.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/exec/exec-all.h | 19 +------------------
>> include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++
>> 2 files changed, 32 insertions(+), 18 deletions(-)
>> create mode 100644 include/exec/helper-getpc.h
>
> Preferably include/accel/tcg/getpc.h or similar
Also these should be guarded for CONFIG_TCG IMHO, similar to
include/exec/cpu_ldst.h:
#ifndef CONFIG_TCG
#error Can only include this header with TCG
#endif
If cleanups are required, I can deal with them later.
> otherwise:
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 15/16] accel/tcg: Build tcg-runtime.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (14 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 14/16] include/exec: Split out helper-getpc.h Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:13 ` Pierrick Bouvier
2025-03-07 18:56 ` [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Richard Henderson
` (2 subsequent siblings)
18 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.c | 8 ++------
accel/tcg/meson.build | 2 +-
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 9fa539ad3d..72c4c6bd31 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -23,13 +23,9 @@
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
-#include "cpu.h"
+#include "exec/cpu-common.h"
#include "exec/helper-proto-common.h"
-#include "exec/cpu_ldst.h"
-#include "exec/exec-all.h"
-#include "disas/disas.h"
-#include "exec/log.h"
-#include "tcg/tcg.h"
+#include "exec/helper-getpc.h"
#define HELPER_H "accel/tcg/tcg-runtime.h"
#include "exec/helper-info.c.inc"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 81fb25da5c..411fe28dea 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,5 +1,6 @@
common_ss.add(when: 'CONFIG_TCG', if_true: files(
'cpu-exec-common.c',
+ 'tcg-runtime.c',
))
tcg_specific_ss = ss.source_set()
tcg_specific_ss.add(files(
@@ -7,7 +8,6 @@ tcg_specific_ss.add(files(
'cpu-exec.c',
'tb-maint.c',
'tcg-runtime-gvec.c',
- 'tcg-runtime.c',
'translate-all.c',
'translator.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 15/16] accel/tcg: Build tcg-runtime.c once
2025-03-07 18:56 ` [PATCH 15/16] accel/tcg: Build tcg-runtime.c once Richard Henderson
@ 2025-03-07 19:13 ` Pierrick Bouvier
0 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-runtime.c | 8 ++------
> accel/tcg/meson.build | 2 +-
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
> index 9fa539ad3d..72c4c6bd31 100644
> --- a/accel/tcg/tcg-runtime.c
> +++ b/accel/tcg/tcg-runtime.c
> @@ -23,13 +23,9 @@
> */
> #include "qemu/osdep.h"
> #include "qemu/host-utils.h"
> -#include "cpu.h"
> +#include "exec/cpu-common.h"
> #include "exec/helper-proto-common.h"
> -#include "exec/cpu_ldst.h"
> -#include "exec/exec-all.h"
> -#include "disas/disas.h"
> -#include "exec/log.h"
> -#include "tcg/tcg.h"
> +#include "exec/helper-getpc.h"
>
> #define HELPER_H "accel/tcg/tcg-runtime.h"
> #include "exec/helper-info.c.inc"
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 81fb25da5c..411fe28dea 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -1,5 +1,6 @@
> common_ss.add(when: 'CONFIG_TCG', if_true: files(
> 'cpu-exec-common.c',
> + 'tcg-runtime.c',
> ))
> tcg_specific_ss = ss.source_set()
> tcg_specific_ss.add(files(
> @@ -7,7 +8,6 @@ tcg_specific_ss.add(files(
> 'cpu-exec.c',
> 'tb-maint.c',
> 'tcg-runtime-gvec.c',
> - 'tcg-runtime.c',
> 'translate-all.c',
> 'translator.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (15 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 15/16] accel/tcg: Build tcg-runtime.c once Richard Henderson
@ 2025-03-07 18:56 ` Richard Henderson
2025-03-07 19:14 ` Pierrick Bouvier
2025-03-07 21:55 ` Philippe Mathieu-Daudé
2025-03-07 20:13 ` [PATCH 00/16] accel/tcg: Compile more files once Pierrick Bouvier
2025-03-07 21:42 ` Philippe Mathieu-Daudé
18 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2025-03-07 18:56 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime-gvec.c | 1 -
accel/tcg/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index afca89baa1..ff927c5dd8 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
-#include "cpu.h"
#include "exec/helper-proto-common.h"
#include "tcg/tcg-gvec-desc.h"
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 411fe28dea..38ff227eb0 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,13 +1,13 @@
common_ss.add(when: 'CONFIG_TCG', if_true: files(
'cpu-exec-common.c',
'tcg-runtime.c',
+ 'tcg-runtime-gvec.c',
))
tcg_specific_ss = ss.source_set()
tcg_specific_ss.add(files(
'tcg-all.c',
'cpu-exec.c',
'tb-maint.c',
- 'tcg-runtime-gvec.c',
'translate-all.c',
'translator.c',
))
--
2.43.0
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once
2025-03-07 18:56 ` [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Richard Henderson
@ 2025-03-07 19:14 ` Pierrick Bouvier
2025-03-07 21:55 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 19:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-runtime-gvec.c | 1 -
> accel/tcg/meson.build | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
> index afca89baa1..ff927c5dd8 100644
> --- a/accel/tcg/tcg-runtime-gvec.c
> +++ b/accel/tcg/tcg-runtime-gvec.c
> @@ -19,7 +19,6 @@
>
> #include "qemu/osdep.h"
> #include "qemu/host-utils.h"
> -#include "cpu.h"
> #include "exec/helper-proto-common.h"
> #include "tcg/tcg-gvec-desc.h"
>
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 411fe28dea..38ff227eb0 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -1,13 +1,13 @@
> common_ss.add(when: 'CONFIG_TCG', if_true: files(
> 'cpu-exec-common.c',
> 'tcg-runtime.c',
> + 'tcg-runtime-gvec.c',
> ))
> tcg_specific_ss = ss.source_set()
> tcg_specific_ss.add(files(
> 'tcg-all.c',
> 'cpu-exec.c',
> 'tb-maint.c',
> - 'tcg-runtime-gvec.c',
> 'translate-all.c',
> 'translator.c',
> ))
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once
2025-03-07 18:56 ` [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Richard Henderson
2025-03-07 19:14 ` Pierrick Bouvier
@ 2025-03-07 21:55 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 21:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/tcg-runtime-gvec.c | 1 -
> accel/tcg/meson.build | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
💞
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 00/16] accel/tcg: Compile more files once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (16 preceding siblings ...)
2025-03-07 18:56 ` [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Richard Henderson
@ 2025-03-07 20:13 ` Pierrick Bouvier
2025-03-07 21:42 ` Philippe Mathieu-Daudé
18 siblings, 0 replies; 37+ messages in thread
From: Pierrick Bouvier @ 2025-03-07 20:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: philmd
On 3/7/25 10:56, Richard Henderson wrote:
> Take care of some easy cases in accel/tcg/.
> From here it starts getting harder. :-)
>
It would be convenient to work on top of it.
Could you rebase it on top of master?
Thanks,
Pierrick
>
> r~
>
>
> Philippe Mathieu-Daudé (6):
> exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'
> exec: Declare tlb_set_page_full() in 'exec/cputlb.h'
> exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'
> exec: Declare tlb_set_page() in 'exec/cputlb.h'
> exec: Declare tlb_hit*() in 'exec/cputlb.h'
> exec: Declare tlb_flush*() in 'exec/cputlb.h'
>
> Richard Henderson (10):
> include/exec: Split out exec/cpu-interrupt.h
> accel/tcg: Compile watchpoint.c once
> system: Build watchpoint.c once
> accel/tcg: Build tcg-accel-ops.c once
> accel/tcg: Build tcg-accel-ops-icount.c once
> accel/tcg: Build tcg-accel-ops-rr.c once
> accel/tcg: Build tcg-accel-ops-mttcg.c once
> include/exec: Split out helper-getpc.h
> accel/tcg: Build tcg-runtime.c once
> accel/tcg: Build tcg-runtime-gvec.c once
>
> accel/tcg/internal-common.h | 2 +
> accel/tcg/tb-internal.h | 2 -
> include/exec/cpu-all.h | 76 +-------
> include/exec/cpu-interrupt.h | 70 +++++++
> include/exec/cputlb.h | 263 ++++++++++++++++++++++++++-
> include/exec/exec-all.h | 262 +-------------------------
> include/exec/helper-getpc.h | 31 ++++
> include/exec/poison.h | 13 --
> include/exec/ram_addr.h | 1 +
> accel/tcg/cputlb.c | 23 +++
> accel/tcg/tcg-accel-ops-icount.c | 2 +-
> accel/tcg/tcg-accel-ops-mttcg.c | 1 -
> accel/tcg/tcg-accel-ops-rr.c | 2 +-
> accel/tcg/tcg-accel-ops.c | 2 +-
> accel/tcg/tcg-runtime-gvec.c | 1 -
> accel/tcg/tcg-runtime.c | 8 +-
> accel/tcg/watchpoint.c | 5 +-
> cpu-target.c | 1 +
> hw/intc/armv7m_nvic.c | 2 +-
> hw/ppc/spapr_nested.c | 1 +
> hw/sh4/sh7750.c | 1 +
> system/physmem.c | 1 +
> system/watchpoint.c | 3 +-
> target/alpha/helper.c | 2 +-
> target/alpha/sys_helper.c | 2 +-
> target/arm/helper.c | 1 +
> target/arm/tcg/tlb-insns.c | 2 +-
> target/avr/helper.c | 2 +-
> target/hppa/mem_helper.c | 1 +
> target/i386/helper.c | 2 +-
> target/i386/machine.c | 2 +-
> target/i386/tcg/fpu_helper.c | 2 +-
> target/i386/tcg/misc_helper.c | 2 +-
> target/i386/tcg/system/excp_helper.c | 2 +-
> target/i386/tcg/system/misc_helper.c | 2 +-
> target/i386/tcg/system/svm_helper.c | 2 +-
> target/loongarch/tcg/csr_helper.c | 2 +-
> target/loongarch/tcg/tlb_helper.c | 1 +
> target/m68k/helper.c | 1 +
> target/microblaze/helper.c | 2 +-
> target/microblaze/mmu.c | 2 +-
> target/mips/system/cp0.c | 2 +-
> target/mips/tcg/system/cp0_helper.c | 2 +-
> target/mips/tcg/system/tlb_helper.c | 1 +
> target/openrisc/mmu.c | 2 +-
> target/openrisc/sys_helper.c | 1 +
> target/ppc/helper_regs.c | 2 +-
> target/ppc/misc_helper.c | 1 +
> target/ppc/mmu_helper.c | 1 +
> target/riscv/cpu_helper.c | 1 +
> target/riscv/csr.c | 1 +
> target/riscv/op_helper.c | 1 +
> target/riscv/pmp.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/gdbstub.c | 2 +-
> target/s390x/sigp.c | 1 +
> target/s390x/tcg/excp_helper.c | 1 +
> target/s390x/tcg/mem_helper.c | 1 +
> target/s390x/tcg/misc_helper.c | 1 +
> target/sh4/helper.c | 1 +
> target/sparc/ldst_helper.c | 1 +
> target/sparc/mmu_helper.c | 2 +-
> target/tricore/helper.c | 2 +-
> target/xtensa/helper.c | 2 +-
> target/xtensa/mmu_helper.c | 1 +
> accel/tcg/meson.build | 14 +-
> system/meson.build | 2 +-
> 67 files changed, 450 insertions(+), 405 deletions(-)
> create mode 100644 include/exec/cpu-interrupt.h
> create mode 100644 include/exec/helper-getpc.h
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 00/16] accel/tcg: Compile more files once
2025-03-07 18:56 [PATCH 00/16] accel/tcg: Compile more files once Richard Henderson
` (17 preceding siblings ...)
2025-03-07 20:13 ` [PATCH 00/16] accel/tcg: Compile more files once Pierrick Bouvier
@ 2025-03-07 21:42 ` Philippe Mathieu-Daudé
18 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-07 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/3/25 19:56, Richard Henderson wrote:
> Philippe Mathieu-Daudé (6):
> exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'
> exec: Declare tlb_set_page_full() in 'exec/cputlb.h'
> exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'
> exec: Declare tlb_set_page() in 'exec/cputlb.h'
> exec: Declare tlb_hit*() in 'exec/cputlb.h'
> exec: Declare tlb_flush*() in 'exec/cputlb.h'
Thanks for taking these...
I'll rebase my "move that API to softmmu/tlb.h' on top, the
other patches left in my previous series becoming 'move to
softmmu/probe.h'.
^ permalink raw reply [flat|nested] 37+ messages in thread