[Qemu-devel] [PATCH] undefined instruction handling to fix for ARM

[Jason Wessel <jason.wessel@windriver.com>]

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After some significant debugging I found the problem with GDB on the 
target side.

The instruction translation was not correctly executing undefined 
instructions per section 3.13.1 of the ARM Architecture Reference 
Manual.  Using the attached patch, the target side GDB as well as kernel 
side ptrace() with software breakpoints execute correctly and report 
exceptions to the correct vector.

Thanks,
Jason.

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? .pc
? patches
Index: Changelog
===================================================================
RCS file: /sources/qemu/qemu/Changelog,v
retrieving revision 1.115
diff -u -r1.115 Changelog
--- Changelog	30 Apr 2006 21:28:35 -0000	1.115
+++ Changelog	2 May 2006 20:14:20 -0000
@@ -8,6 +8,8 @@
   - Solaris port (Ben Taylor)
   - Preliminary SH4 target (Samuel Tardieu)
   - VNC server (Anthony Liguori)
+  - Fix undefined instruction handling
+    for gdb and soft stepping (Jason Wessel)
 
 version 0.8.0:
 
Index: target-arm/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-arm/translate.c,v
retrieving revision 1.41
diff -u -r1.41 translate.c
--- target-arm/translate.c	9 Apr 2006 14:38:57 -0000	1.41
+++ target-arm/translate.c	2 May 2006 20:14:20 -0000
@@ -1589,6 +1589,15 @@
         case 0x5:
         case 0x6:
         case 0x7:
+            /* Check for undefined extension instructions 
+             * per the ARM Bible IE:
+             * xxxx 0111 1111 xxxx  xxxx xxxx 1111 xxxx
+             */
+            sh = (0xf << 20) | (0xf << 4); 
+            if (op1 == 0x7 && ((insn & sh) == sh))
+            {
+                goto illegal_op;
+            }
             /* load/store byte/word */
             rn = (insn >> 16) & 0xf;
             rd = (insn >> 12) & 0xf;