From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Fb1LJ-0008LK-VM for qemu-devel@nongnu.org; Tue, 02 May 2006 16:19:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Fb1LI-0008Kn-Un for qemu-devel@nongnu.org; Tue, 02 May 2006 16:19:33 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Fb1LI-0008Ki-Nx for qemu-devel@nongnu.org; Tue, 02 May 2006 16:19:32 -0400 Received: from [147.11.1.11] (helo=mail.wrs.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1Fb1LW-0002mR-CR for qemu-devel@nongnu.org; Tue, 02 May 2006 16:19:46 -0400 Received: from ala-mail04.corp.ad.wrs.com (ala-mail04 [147.11.57.145]) by mail.wrs.com (8.13.6/8.13.3) with ESMTP id k42KJRXq021926 for ; Tue, 2 May 2006 13:19:28 -0700 (PDT) Message-ID: <4457BECF.5080804@windriver.com> Date: Tue, 02 May 2006 15:19:27 -0500 From: Jason Wessel MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------090407070302030207080807" Subject: [Qemu-devel] [PATCH] undefined instruction handling to fix for ARM Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------090407070302030207080807 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit After some significant debugging I found the problem with GDB on the target side. The instruction translation was not correctly executing undefined instructions per section 3.13.1 of the ARM Architecture Reference Manual. Using the attached patch, the target side GDB as well as kernel side ptrace() with software breakpoints execute correctly and report exceptions to the correct vector. Thanks, Jason. --------------090407070302030207080807 Content-Type: text/plain; name="undefined_instruction_handler_fix.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="undefined_instruction_handler_fix.patch" ? .pc ? patches Index: Changelog =================================================================== RCS file: /sources/qemu/qemu/Changelog,v retrieving revision 1.115 diff -u -r1.115 Changelog --- Changelog 30 Apr 2006 21:28:35 -0000 1.115 +++ Changelog 2 May 2006 20:14:20 -0000 @@ -8,6 +8,8 @@ - Solaris port (Ben Taylor) - Preliminary SH4 target (Samuel Tardieu) - VNC server (Anthony Liguori) + - Fix undefined instruction handling + for gdb and soft stepping (Jason Wessel) version 0.8.0: Index: target-arm/translate.c =================================================================== RCS file: /sources/qemu/qemu/target-arm/translate.c,v retrieving revision 1.41 diff -u -r1.41 translate.c --- target-arm/translate.c 9 Apr 2006 14:38:57 -0000 1.41 +++ target-arm/translate.c 2 May 2006 20:14:20 -0000 @@ -1589,6 +1589,15 @@ case 0x5: case 0x6: case 0x7: + /* Check for undefined extension instructions + * per the ARM Bible IE: + * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx + */ + sh = (0xf << 20) | (0xf << 4); + if (op1 == 0x7 && ((insn & sh) == sh)) + { + goto illegal_op; + } /* load/store byte/word */ rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; --------------090407070302030207080807--